SoC Cache Controller Redirecting DRAM Defective Codeword Access
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Solution Overview
Problem
As DRAM process technology scales down, there is a challenge in maintaining data reliability due to decreased cell capacitance, increased cell transistor leakage, and variance in cell retention, leading to potential errors and increased refresh frequency or error correction needs, which impact memory bandwidth and power consumption.
Innovation Solution
A system and method that utilize a cache on a System on Chip (SoC) to store error-corrected data for failed physical codeword addresses, redirecting memory transactions from DRAM to the cache to prevent further access to defective cells, thereby maintaining data integrity and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM process technology is scaled down to increase memory capacity, then memory capacity and density are improved, but cell capacitance decreases and transistor leakage increases leading to data reliability degradation
Solution Approach 1:
The patent introduces an intermediary error correction mechanism that acts as a mediator between the degraded DRAM cells and the data storage function. Error correction codes (ECC) are implemented to detect and correct bit errors in data stored in scaled-down DRAM cells, allowing the system to maintain data reliability despite reduced cell capacitance and increased leakage at smaller process nodes
Solution Approach 2:
The patent changes operational parameters including increasing refresh frequency and adjusting voltage levels to compensate for the degraded cell characteristics at scaled dimensions. By dynamically adjusting these parameters, the system maintains adequate data retention and reliability in smaller-capacitance cells while preserving the benefits of process scaling
2Reliability
If refresh frequency is increased to maintain data retention in scaled DRAM cells, then data reliability is improved, but memory bandwidth and power consumption deteriorate
Solution Approach 1:
The patent applies local quality by implementing selective refresh strategies where only specific memory regions or banks that exhibit degradation are refreshed at higher frequencies, while other regions operate at normal refresh rates. This localized approach maintains data retention in problematic areas without unnecessarily reducing bandwidth or increasing power consumption across the entire memory array
3Reliability
If block error correction is implemented to correct multiple simultaneous errors, then data reliability is improved, but silicon area and device complexity increase
Solution Approach 1:
The patent implements partial error correction by focusing on correcting the most probable and critical error patterns rather than providing exhaustive correction for all possible error combinations. This selective approach achieves adequate reliability for the application while using fewer redundant bits and simpler correction logic, thereby reducing the silicon area and complexity overhead compared to comprehensive multiple-error correction schemes
Data Source
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AI summary
Systems, methods, and computer programs are disclosed for resolving dynamic random access memory (DRAM) defects. One embodiment is a system comprising a dynamic random access memory (DRAM) system electrically coupled to a system on chip (SoC). The SoC comprises a cache and a cache controller. The cache controller is configured to store corrected data for a failed physical codeword address associated with the DRAM in the cache and provide further access to the failed physical codeword address from the cache instead of the DRAM system.