SoC Cache Flush Control for Runtime Push to Persistence
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Solution Overview
Problem
Existing systems-on-chip (SOCs) face challenges in ensuring data durability and visibility during unexpected shutdowns due to their complexity, making it difficult for application programs and operating systems to effectively flush cache data to persistent memory without disrupting operations.
Innovation Solution
A system-on-chip with a microsequencer that offloads the task of recognizing and responding to runtime global push to persistence requirements, causing caches to flush dirty data to external memory and completing in-flight memory operations, using hardware triggers for terminal and non-terminal events to ensure data durability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If application programs and operating systems manually flush cache data to persistent memory to ensure data durability during unexpected shutdowns, then data preservation reliability is improved, but system complexity and operational disruption increase
Solution Approach 1:
The system automatically detects terminal events (power loss, reset) and triggers cache flush operations without requiring application program or operating system intervention. The microsequencer monitors system state and autonomously initiates the data preservation sequence, making the system self-protecting against data loss.
Solution Approach 2:
A microsequencer is introduced as an intermediary component between the data processor and cache system. This microsequencer receives terminal event triggers, stalls the data processor, and coordinates the cache flush operation, simplifying the interface for higher-level software while ensuring reliable data preservation.
2Reliability
If the system flushes cache data to persistent memory upon detecting terminal events, then data durability is improved, but processing speed and operational continuity deteriorate
Solution Approach 1:
The system maintains cache data in a modified state during normal operation, deferring the flush operation until a terminal event is detected. This allows high-speed processing to continue uninterrupted, with data durability ensured only when necessary by flushing to persistent memory at the moment of shutdown detection.
Solution Approach 2:
The system dynamically adjusts its behavior based on system state: during normal operation, it maintains high processing speed by keeping data in cache; upon detecting a terminal event, it transitions to data preservation mode by stalling the processor and flushing cache contents to persistent memory.
3Reliability
If the system implements comprehensive cache flushing mechanisms for all processors, then data visibility and durability are improved, but power consumption and operational disruption increase
Solution Approach 1:
Instead of continuously monitoring and flushing cache data, the system employs periodic action triggered only by specific terminal events (power loss detection, reset signals). The microsequencer remains in a low-power state during normal operation and activates cache flush operations only when triggered by these periodic event checks.
Data Source
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AI summary
A system-on-chip with runtime global push to persistence includes a data processor having a cache, an external memory interface, and a microsequencer. The external memory interface is coupled to the cache and is adapted to be coupled to an external memory. The cache provides data to the external memory interface for storage in the external memory. The microsequencer is coupled to the data processor. In response to a trigger signal, the microsequencer causes the cache to flush the data by sending the data to the external memory interface for transmission to the external memory.