SoC Cache Stashing via Queue Manager to Prevent Thrashing
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Solution Overview
Problem
Conventional packet processing systems experience significant latency due to expensive access to external system memory, and cache thrashing occurs when the packet arrival rate exceeds processing capacity, leading to increased read latency and cache overflow.
Innovation Solution
A queue manager-based system that stashes packets into the cache only when the egress queue fill level falls below a threshold, preventing cache thrashing by controlling the flow of packet descriptors between ingress and egress queues and prioritizing cache storage for latency-sensitive packets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If packets are stashed into cache to reduce system memory access latency, then packet processing latency is reduced, but cache thrashing occurs when packet arrival rate exceeds processing capacity
Solution Approach 1:
The patent implements dynamic cache management by making the cache stashable area configurable and adjustable. The system dynamically allocates cache resources based on traffic patterns and processing capacity, allowing the cache stashable area to be modified during operation to prevent thrashing while maintaining low latency performance.
Solution Approach 2:
The patent employs feedback mechanisms where the system monitors cache usage patterns and packet processing rates, then adjusts the cache stashable area configuration accordingly. This feedback loop prevents cache thrashing by reducing the stashable area when processing capacity is exceeded, while maintaining optimal performance during normal operation.
2Quantity of substance
If the cache stashable area is increased to handle burst packets, then cache capacity is improved, but cache thrashing is exacerbated
Solution Approach 1:
The system dynamically adjusts the cache stashable area based on real-time monitoring of packet arrival rates and processing capacity. During burst traffic, the stashable area is reduced to prevent thrashing, while during normal operation it is increased to handle incoming packets efficiently, optimizing cache capacity utilization without exacerbating thrashing.
Solution Approach 2:
The patent changes the parameter of cache stashable area size based on system conditions. By modifying this parameter dynamically rather than using a fixed large capacity, the system avoids cache thrashing during bursts while maintaining sufficient capacity during normal operation.
3Productivity
If packets are cached without regard to processing capacity, then packet processing speed is improved, but system complexity increases due to cache management overhead
Solution Approach 1:
The patent extracts the cache management complexity from the main packet processing path by implementing a separate configuration and control mechanism. The cache stashable area is managed independently through dedicated control logic, allowing simple packet processing operations to benefit from caching without being burdened by complex cache management overhead.
Data Source
AI summary
In a system-on-chip (SoC) including a processor, a method is provided for stashing packet information that prevents cache thrashing. In operation, an Ethernet subsystem accepts a plurality of packets and sends the packets to an external memory for storage. A packet descriptor is derived for each accepted packet and is added to an ingress queue. Packet descriptors are transferred from the ingress queue to an egress queue supplying the packet descriptors to a processor. A context manager monitors the fill level of packet descriptors in the egress queue. In response to monitoring the fill level, the context manager stashes packets from the external memory into a cache, where each stashed packet is associated with a packet descriptor in the egress queue. Packet descriptors are transferred from the ingress queue to the egress queue in response to a number of packet descriptors in the egress queue falling below the fill level.