SoC Carrier Structure with Custom Interface for Pin Reduction
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Solution Overview
Problem
The complex circuit structure of System-on-Chip (SoC) devices leads to high manufacturing costs and prolonged development cycles due to the full custom process from design to manufacturing, which is time-consuming and labor-intensive, especially since system developers handle all stages independently.
Innovation Solution
A carrier structure with a custom interface is introduced, where a common die tested and certified in advance is integrated with a substrate, allowing only the expansive die to be tested, reducing development procedures and costs, and featuring built-in electrical connections to minimize external pins, enabling mass production and simplifying the SoC structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a full custom process is adopted from design to manufacturing, then system developers have complete control and customization capability, but the costs of manpower and time are considerable
Solution Approach 1:
The SoC development process is segmented into two parts: a common die (carrier structure) that is pre-manufactured and tested, and an expansive die that is custom-designed. This segmentation allows the time-consuming manufacturing and testing processes to be performed once on the common die, while only the expansive die requires custom development, thereby reducing the overall development cycle while maintaining customization capability.
Solution Approach 2:
The common die is manufactured, tested, and certified in advance before being integrated with the expansive die. This preliminary action eliminates the need to repeat manufacturing and testing for each custom SoC configuration, significantly reducing the development time and manpower costs while preserving the ability to customize the expansive die.
2Adaptability or versatility
If a full custom process is adopted from design to manufacturing, then system developers have complete control, but the costs of manpower are considerable
Solution Approach 1:
The SoC is divided into a common die and an expansive die. The common die is manufactured using standardized processes that can be mass-produced, reducing per-unit manufacturing costs. The expansive die is manufactured separately with custom specifications. This segmentation allows economies of scale to be achieved in the common die production while maintaining customization in the expansive die.
Solution Approach 2:
The common die is designed to be universal and compatible with multiple different expansive dies through standardized interfaces and carrier structures. This universality allows the same common die to be reused across different product configurations, amortizing the manufacturing and development costs over multiple products and reducing the overall cost per unit.
3Adaptability or versatility
If all elements and structures are determined independently by system developers, then full customization is achieved, but the developing procedures are complex and time-consuming
Solution Approach 1:
The complex SoC circuit structure is segmented into a standardized common die and a custom expansive die. The common die contains standardized elements and interfaces that simplify the overall design process, while the expansive die contains only the custom elements needed for specific applications. This segmentation reduces the complexity of the customization process by limiting the scope of elements that need to be independently designed.
4Device complexity
If common dies are integrated with substrate with built-in electrical connections, then the number of pins for external connection is reduced, but the structure becomes more integrated
Solution Approach 1:
The common die is integrated with the substrate through carrier structures that provide built-in electrical connections. This merging of the common die and substrate into a single assembly reduces the number of external pins needed, simplifies the overall structure, and eliminates the need for separate connection processes, thereby reducing manufacturing complexity despite the integrated nature.
Data Source
AI summary
The present invention discloses a carrier structure of a System-on-Chip (SoC) with a custom interface. The carrier structure includes a substrate, at least one common die, at least one custom interface and a molding compound. The common die and the custom interface are disposed on the substrate. The molding compound is used to package the common die which electrically connects to the substrate and the custom interface respectively. The carrier structure which includes the common die can form a complete SoC by connecting to an expansive die through the custom interface. The carrier structure with the common die which can be tested and certified in advance allows reducing and simplifying the developing procedures of the SoC.