SoC Clock Control for Active-Idle Frequency Switching
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Solution Overview
Problem
System-on-chip (SoC) devices consume unnecessary power when operating clock signals are not adjusted according to the state of function blocks, leading to reduced battery lifespan due to inconsistent frequency usage across active and idle modes.
Innovation Solution
Implementing a clock controller that dynamically adjusts the operating frequency of function blocks based on their state, decreasing frequency when transitioning from active to idle and increasing when transitioning from idle to active, using a mode detector and divider controller to manage reference clock signals and set appropriate frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the operating clock signal frequency is maintained at a high level for all function blocks regardless of their state, then the system can respond quickly when function blocks transition to active state, but unnecessary power is consumed when function blocks are in idle mode
Solution Approach 1:
The patent applies dynamics by making the clock signal frequency adjustable based on the operational state of function blocks. The system dynamically transitions between high frequency (when active) and low frequency (when idle), allowing the clock frequency to adapt to the real-time needs of the system rather than remaining fixed at a high level.
Solution Approach 2:
The patent changes the frequency parameter of the clock signal based on the operational state of function blocks. By detecting whether a function block is in active or idle mode, the system adjusts the clock frequency accordingly - maintaining high frequency for rapid response when needed, and reducing to low frequency to minimize power consumption during idle periods.
2Use of energy by moving object
If the operating clock signal frequency is decreased for idle function blocks, then power consumption is reduced, but voltage drops may occur during transitions from idle to active state
Solution Approach 1:
The patent applies preliminary action by providing a wake-up clock signal at a high frequency before the function block fully transitions to active mode. This preliminary high-frequency clock signal ensures that the function block is ready to operate immediately upon activation, preventing functional delays or reliability issues that could arise from sudden frequency transitions.
Solution Approach 2:
The patent uses periodic action by implementing a multi-stage frequency transition process. Instead of a single abrupt frequency change, the system cycles through different frequency levels (low frequency during idle, intermediate wake-up frequency during transition, and high frequency during active operation), ensuring smooth transitions and maintaining reliability.
3Use of energy by moving object
If different clock signal frequencies are applied to function blocks based on their operational state, then power consumption is optimized, but the system complexity increases due to additional control circuits
Solution Approach 1:
The patent applies segmentation by dividing the clock signal distribution system into separate paths: a main clock signal path for active function blocks and a wake-up clock signal path for transitioning function blocks. This segmentation allows independent control of clock frequencies for different operational states without requiring a completely complex unified control system.
Solution Approach 2:
The patent uses an intermediary approach by introducing a wake-up clock signal as a intermediate step between the low-frequency idle clock and the high-frequency active clock. This intermediary signal simplifies the transition process and reduces the complexity of direct frequency switching while still achieving power optimization.
Data Source
AI summary
A system-on-chip includes a clock controller configured to decrease an operating frequency of at least one function block based on a change in an operating state of the at least one function block from an active state to an idle state. In a method of operating a system-on-chip including at least one function block, an operating frequency of the at least one function block is decreased based on a change in an operating state of the at least one function block from an active state to an idle state. The decreased operating frequency is greater than zero.