SOC Clock Controller Dynamic Power Management
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Solution Overview
Problem
Portable electronic devices face challenges in supporting prolonged high power consumption due to battery limitations, necessitating effective power absorption control and performance optimization to prevent energy waste and performance degradation.
Innovation Solution
A System On Chip (SOC) circuit configuration incorporating a consumption detector and a clock controller with set clock division factors to manage current consumption by comparing absorbed current with threshold values and adjusting operating frequencies, facilitating a balance between power usage and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high power consumption conditions are maintained to support device performance, then device performance is improved, but battery life is reduced
Solution Approach 1:
The patent implements dynamic power management by continuously monitoring current consumption and adapting clock division factors in real-time. The system transitions between different power states based on detected consumption levels, making the power consumption dynamic rather than static, thus resolving the contradiction between maintaining high performance and extending battery life.
Solution Approach 2:
The system changes operational parameters (clock division factors) based on detected current consumption levels. When consumption exceeds thresholds, the system modifies clock division ratios to reduce power usage. This parameter adaptation allows the system to balance performance and battery life by adjusting operational characteristics according to actual power availability.
2Duration of action of moving object
If current consumption is reduced to extend battery life, then battery life is improved, but device performance may degrade
Solution Approach 1:
The patent employs a feedback mechanism where current consumption is continuously detected and fed back to the clock controller. Based on this feedback, the system adjusts clock division factors to optimize power consumption. This closed-loop control ensures that performance is reduced only when necessary, maintaining the best possible balance between battery life extension and device functionality.
Solution Approach 2:
The system applies partial power reduction measures by selectively adjusting clock division factors for different functional blocks rather than uniformly reducing power across the entire system. This allows critical functions to maintain higher performance levels while non-critical functions operate at reduced power levels, achieving battery life extension without excessive performance degradation.
3Use of energy by moving object
If clock division factors are increased to reduce power consumption, then power consumption is reduced, but operating frequency decreases
Solution Approach 1:
The patent applies different clock division factors to different functional blocks or domains within the system rather than using a uniform division ratio. This local differentiation allows critical high-speed functions to maintain higher operating frequencies while non-critical functions operate at lower frequencies with higher division ratios, achieving overall power reduction without uniformly degrading system performance.
Data Source
AI summary
A system on chip, SOC circuit comprising a plurality of peripherals configured to be clocked with respective clock signals, wherein the circuit comprises a clock controller configured to produce said respective clock signals via respective clock divide factors, the clock controller comprising a plurality of storage locations having stored therein respective sets of clock divide factors, wherein the clock controller comprises clock divide factor selection circuitry configured to select an operating set of clock divide factors out of said respective sets of clock divide factors stored in said plurality of storage locations and wherein the clock controller is configured to apply to the plurality of peripherals respective clock signals produced via the clock divide factors in the operating set of clock divide factors selected out of said respective sets of clock divide factors stored in said plurality of storage locations.