SoC Clock Gating with Chained Dividers for Glitch-Free Switching
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Solution Overview
Problem
Existing clock control mechanisms in System on a Chip (SoC) result in clock glitches when clocks are turned on or off, leading to issues such as bad state stop conditions and timing violations in digital circuitry.
Innovation Solution
A clock control circuit that includes a chain of D flip flops, AND gates, and additional wakeup delay circuitry to ensure clocks are released and stopped without glitches by synchronizing the clock enable signal with the falling edges of the clock signal, using a wakeup counter or condition estimators to determine stable clock states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If clocks are turned on or off during operation, then power consumption is reduced or chip activity is optimized, but clock glitches occur causing circuit malfunction and timing violations
Solution Approach 1:
The patent applies preliminary action by asserting the clock enable signal before actually enabling the clock. This allows the circuit to prepare for clock activation in advance, ensuring that all dependent circuits are ready to receive the clock signal without glitches. The clock enable signal is asserted early enough to prevent timing violations while the clock itself remains disabled until ready.
Solution Approach 2:
The patent introduces an intermediary mechanism in the form of a clock control circuit that mediates between the clock source and the rest of the circuit. This control circuit includes logic that monitors system readiness and only enables the clock when appropriate, acting as a buffer that prevents direct glitch propagation to sensitive digital circuits.
2Ease of operation
If clock control is simplified to allow easy turning on and off, then ease of operation improves, but clock glitches occur causing bad state stop conditions and timing violations
Solution Approach 1:
The patent implements feedback by monitoring the state of circuits dependent on the clock and using this information to control clock enabling. The clock control circuit receives feedback about system readiness and adjusts clock activation accordingly, ensuring that clocks are only enabled when all dependent circuits are in appropriate states, thus preventing timing violations while maintaining simple control interfaces.
Data Source
AI summary
A plurality of chained clock dividers provides a plurality of generated clocks generated from a root clock. Each clock divider provides a generated clock having a lower frequency that its corresponding input clock and which transitions at falling edges of its corresponding input clock. Clock gating circuitry selectively gates the generated clocks based on a clock ready signal and provides the generated clocks as a corresponding plurality of safe clocks when the clock ready indicator indicates the generated clocks are ready. A delay circuit has an inverted clock input configured to receive a final generated clock. The delay circuit provides a trigger output in response to a falling edge of the final generated clock. A set of synchronization flip flops receives a clock enable signal and the trigger output and provides the clock ready indicator based on the clock enable signal and the trigger output.