SoC Memory Interconnect Clock Gating for Low-Power Access
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Solution Overview
Problem
Existing systems on chip (SoCs) face challenges in efficiently managing power consumption during lower-power modes, particularly in synchronizing components to optimize idle periods and reduce power usage without compromising performance.
Innovation Solution
Implementing a power controller that manages root clock gating and dynamic voltage and frequency scaling (DVFS) to synchronize components, periodically gating the system interconnect circuit clock signal based on activity requests, and transitioning the memory to a self-refresh mode during idle periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the memory operates at high speed continuously, then the access speed requirement is met, but the power consumption increases significantly
Solution Approach 1:
The patent implements periodic clock gating of the memory controller to enable the memory to alternate between high-speed operation modes and low-power standby modes. The memory controller is configured to gate the first clock signal periodically, allowing the memory to operate at high speed during active periods and consume minimal power during gated periods, thus resolving the contradiction between continuous high-speed operation and power consumption.
2Productivity
If the clock signal is continuously provided to the memory controller, then the function modules operate continuously, but the power consumption increases
Solution Approach 1:
The power controller periodically gates the first clock signal to the memory controller, enabling the system to alternate between active operation periods and low-power standby periods. This allows the function modules to maintain continuous operational capability when needed while significantly reducing power consumption during gated periods.
Solution Approach 2:
The system dynamically adjusts its operational state by transitioning between clock-gated and non-gated modes based on operational requirements. The power controller dynamically controls the clock signal to match the operational needs of the function modules, optimizing the balance between productivity and power consumption.
3Reliability
If the memory operates in high-power mode continuously, then data access requirements are met, but the battery life decreases
Solution Approach 1:
The periodic clock gating mechanism allows the memory to maintain high-speed operational reliability during active periods while entering low-power modes during standby periods, thereby extending battery life. The memory controller is configured to gate the clock signal in a periodic manner, ensuring data access reliability is maintained when needed while conserving energy to extend battery life.
Data Source
Figure 1
Figure 2
Figure 3A~3B
AI summary
A system on chip (SoC) and an application processor are provided. The SoC includes a memory controller configured to control a memory; a plurality of function modules configured to access the memory through a memory interface; a system interconnect circuit configured to operate based on a first clock signal and connect the memory interface and the plurality of function modules; and a power controller configured to control the first clock signal to be periodically gated, and control the memory to operate in a lower-power mode during a period in which the first clock signal is gated.