SoC Clock Divider Gating for Glitch-Free Clock Switching
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Solution Overview
Problem
Existing clock control mechanisms in SoCs often result in clock glitches when turning clocks on or off, leading to issues with circuit functionality and timing violations.
Innovation Solution
A clock control circuit that includes a chain of D flip flops and AND gates to generate safe, glitch-free clocks by synchronizing the release and stop of clocks based on predefined conditions, using a wakeup counter and synchronization flip flops to ensure clocks are stable before being released.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If clocks are turned on or off during operation, then power consumption is reduced or circuit activity is optimized, but clock glitches occur causing timing violations and circuit malfunction
Solution Approach 1:
The patent applies preliminary action by checking the phase state of the clock signal before enabling or disabling it. The circuit monitors whether the clock is at a rising edge, falling edge, or steady state, and only allows transitions when the clock is in a safe state (steady low or high), preventing glitches during critical transitions
Solution Approach 2:
The patent introduces an intermediary clock control circuit that sits between the clock source and the rest of the circuit. This intermediary circuit monitors clock phase and controls the enabling/disabling of clocks through AND gates, acting as a mediator that prevents direct switching that would cause glitches
2Adaptability or versatility
If clock switching is allowed during any phase, then clock control flexibility is improved, but timing violations occur due to clock glitches
Solution Approach 1:
The patent implements feedback by continuously monitoring the clock signal phase through D flip-flops that sample the clock at different phases. This feedback information is used to control the clock enable signals, ensuring that clocks are only switched when the feedback indicates a safe phase state, thus maintaining timing accuracy while allowing flexibility
3Adaptability or versatility
If multiple clocks are managed independently, then circuit functionality is improved, but clock synchronization becomes difficult causing potential conflicts
Solution Approach 1:
The patent applies universality by creating a standardized clock control mechanism that can be applied to multiple clocks simultaneously. The same phase-monitoring and enable-control logic is used for all clocks in the system, providing a universal solution that simplifies synchronization while maintaining the ability to manage multiple clocks independently for different circuit functions
Data Source
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AI summary
A plurality of chained clock dividers provides a plurality of generated clocks generated from a root clock. Each clock divider provides a generated clock having a lower frequency that its corresponding input clock and which transitions at falling edges of its corresponding input clock. Clock gating circuity selectively gates the generated clocks based on a clock ready signal and provides the generated clocks as a corresponding plurality of safe clocks when the clock ready indicator indicates the generated clocks are ready. A delay circuit has an inverted clock input configured to receive a final generated clock. The delay circuit provides a trigger output in response to a falling edge of the final generated clock. A set of synchronization flip flops receives a clock enable signal and the trigger output and provides the clock ready indicator based on the clock enable signal and the trigger output.