SoC Clock Management Unit Full Handshake Protocol
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Solution Overview
Problem
Current system-on-chip (SoC) designs continue to supply clock signals unnecessarily, leading to inefficiencies and potential protocol violations in DRAM operations, as they lack a full handshake method for managing clock signals between the clock management unit and intellectual property cores.
Innovation Solution
The implementation of a full handshake method between a clock management unit and logic blocks, including a first and second clock generator, allows for dynamic request and deactivation of clock signals, ensuring clock signals are provided only when needed, using a clock management unit with full handshake circuits to manage and control clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock signals are continuously supplied to IP cores, then operational readiness is maintained, but power consumption increases unnecessarily
Solution Approach 1:
The system dynamically switches between continuous clock supply and clock gating based on operational state. The full handshake mechanism enables the IP core to request clock signals only when needed, allowing the clock management unit to transition from a static continuous supply mode to a dynamic on-demand supply mode, resolving the contradiction between maintaining operational readiness and reducing power consumption
Solution Approach 2:
The full handshake method implements a feedback mechanism where the IP core communicates its clock needs back to the clock management unit through request and acknowledge signals. This feedback loop enables the system to adjust clock supply in real-time based on actual operational requirements, preventing unnecessary power consumption while ensuring clocks are available when needed
2Loss of energy
If clock signals are gated off during idle periods, then power consumption is reduced, but protocol violations may occur in DRAM operations
Solution Approach 1:
The full handshake mechanism provides real-time feedback between the IP core and clock management unit, allowing the system to detect when clock gating might interfere with DRAM protocol requirements. The acknowledge signal ensures the IP core is aware of clock supply status, enabling it to coordinate operations to maintain protocol compliance while still achieving power savings during appropriate idle periods
Solution Approach 2:
The system performs preliminary coordination through the handshake protocol before gating off clock signals. The IP core can initiate clock requests in advance of needed operations, allowing the clock management unit to maintain clocks during critical protocol sequences while gating during truly idle periods, thus preventing protocol violations while maximizing power savings
3Loss of energy
If a full handshake method is implemented for clock signal management, then clock signals are provided only when needed improving power efficiency, but system complexity increases
Solution Approach 1:
The full handshake mechanism is integrated into the existing clock management infrastructure, allowing the same clock management unit to serve both traditional continuous clocking modes and the new on-demand handshake mode. This multi-functionality approach enables power-efficient operation without requiring completely separate clock management hardware, thus reducing the impact on system complexity while achieving significant power savings
Data Source
AI summary
A system-on-chip (SoC) comprises a clock management unit (CMU) including a first clock generator and a second clock generator, the first and second clock generators being configured to generate clock signals. The SoC comprises at least one logic block configured to request the clock signals from the CMU according to a full handshake method and receive the clock signals from the CMU in response to the request. The first clock generator and the second clock generator are configured to communicate according to the full handshake method.