SoC Clock Multiplexing for Flexible PCIe Host Configurations
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Solution Overview
Problem
Existing data center networking systems face challenges in efficiently managing multiple PCIe configurations without requiring circuit board level changes, such as jumper or wire modifications, to support various host connectivity options.
Innovation Solution
Integration of a multiplexer within a system-on-chip (SoC) that supports clock signals from multiple host CPUs, allowing for flexible clock routing configurations without altering the circuit board, thereby supporting multiple PCIe configurations like x16, x8, and x4 without physical changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If external clock multiplexers are used to manage PCIe clocking requirements, then clock signal distribution capability is improved, but device complexity and board space occupation increase
Solution Approach 1:
The patent combines the clock multiplexer functionality directly into the PCIe switch device, merging previously separate components (external clock multiplexer and PCIe switch) into a single integrated unit. This eliminates the need for external clock multiplexers while maintaining clock signal distribution capability, thereby reducing platform complexity and board space occupation.
Solution Approach 2:
The PCIe switch device is designed to perform multiple functions: it acts as both a PCIe switch for data transmission and an integrated clock multiplexer for clock signal distribution. This multi-functionality allows the device to handle both data and clock routing internally, eliminating the need for separate external clock multiplexer components.
2Adaptability or versatility
If external clock multiplexers are used to support multiple host configurations, then clock routing flexibility is improved, but board space and manufacturing cost increase
Solution Approach 1:
The clock multiplexer and PCIe switch are merged into a single device, reducing the total component count on the circuit board. This integration simplifies the manufacturing process by eliminating the need to source, place, and configure separate external clock multiplexer components, thereby reducing manufacturing cost while maintaining clock routing flexibility.
Solution Approach 2:
The integrated PCIe switch device provides universal functionality by handling both data switching and clock multiplexing for multiple host configurations. This multi-functionality allows a single device to support various PCIe configurations (e.g., x16, x8, x4) without requiring additional external components, reducing both board space and manufacturing complexity.
3Adaptability or versatility
If circuit board changes are made to support different PCIe configurations, then configuration adaptability is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The integrated PCIe switch device provides dynamic configuration capability, allowing the system to switch between different PCIe configurations (x16, x8, x4, etc.) through software or firmware control without requiring physical circuit board changes. This dynamic adaptability is achieved through the device's internal routing logic, eliminating the need for manual jumper settings or board reconfiguration.
Solution Approach 2:
The device is designed with universal support for multiple PCIe configurations within a single hardware platform. The integrated clock multiplexer and PCIe switch can handle various lane configurations (x16, x8, x4) simultaneously or individually, providing configuration adaptability without requiring different circuit board designs or additional external components for each configuration mode.
Data Source
AI summary
Examples described herein relate to a system-on-a-chip (SoC) comprising: a multiplexer integrated into the SoC, wherein the multiplexer comprises one or more physical layer (PHY) circuitries and the multiplexer is to receive one or more clock signals and distribute the one or more clock signals to the one or more PHY circuitries based on a clock transfer configuration to support multiple clock distribution schemes. In some examples, the one or more clock signals are received from at least one host comprising one or more of: a central processing unit (CPU), graphics processing unit (GPU), accelerator, memory pool, network-attached appliance, and/or storage device.