SoC Clock Rate Adjustment for Standby Power Reduction
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Solution Overview
Problem
Mobile and portable devices with mobile SoCs face significant power consumption issues during standby mode, as existing technologies fail to effectively minimize power usage in these states.
Innovation Solution
The proposed solution involves a System on a Chip (SoC) design with a power management unit (PMU) that adjusts clock rates for internal and memory interface clock signals based on processor operational states, reducing power consumption by setting clock rates to minimum levels when processors are idle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the SoC is kept powered on during standby mode, then the device can respond quickly to user input, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the clock rate adjustable based on operational state. The internal clock circuit dynamically changes the clock rate from a first clock rate during active operation to a second, lower clock rate during standby mode. This dynamic adjustment allows the system to maintain responsiveness when needed while reducing power consumption during idle periods, resolving the contradiction between response speed and standby power consumption.
2Use of energy by moving object
If the clock rate is reduced to minimum levels during idle states, then standby power consumption is minimized, but the system may not respond quickly enough when activated
Solution Approach 1:
The system dynamically adjusts clock rates based on operational state. During standby, the clock rate is reduced to a second level to minimize power consumption. When activation is detected, the clock rate is quickly restored to a first, higher level, enabling fast response. This dynamic switching resolves the contradiction between minimizing standby power and maintaining quick activation response.
3Productivity
If ancillary components operate at full clock rate continuously, then system performance is maintained, but power consumption increases unnecessarily during standby
Solution Approach 1:
The patent applies dynamics by making the clock rate adjustable based on operational state. The internal clock circuit dynamically changes the clock rate from a first clock rate during active operation to a second, lower clock rate during standby mode. This dynamic adjustment allows the system to maintain responsiveness when needed while reducing power consumption during idle periods, resolving the contradiction between response speed and standby power consumption.
Solution Approach 2:
The patent changes the operational parameter of clock rate based on system state. During active mode, ancillary components operate at a first clock rate to maintain system performance. During standby mode, the clock rate is changed to a second, lower rate to reduce power consumption. This parameter change approach resolves the contradiction between maintaining productivity and reducing energy use.
Data Source
AI summary
System on chip including plurality of processors including first and second processors; plurality of intellectual properties (IPs) including first and second IPs; memory interface; internal clock circuit to receive reference clock signal, generate first internal clock signal, and provide first internal clock signal to first IP; memory interface clock circuit to receive reference clock signal, generate memory interface clock signal, and provide memory interface clock signal to memory interface; and power management unit (PMU), wherein first internal clock signal drives first IP, memory interface clock signal drives memory interface, PMU generates first control signal based on operational states of plurality of processors, and provides first control signal to internal clock circuit, PMU generates second control signal based on operational states of plurality of processors, and provides second control signal to memory interface clock circuit, internal clock circuit sets clock rate of first internal clock signal based on first control signal, and memory interface clock circuit sets clock rate of memory interface clock signal based on second control signal.