SoC Interconnection Clustering With Stacked Memory for NoC Bandwidth
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Solution Overview
Problem
Conventional system-on-chip (SoC) architectures are limited by the performance of interconnects, especially usable bandwidth, and suffer from increased routing complexity due to the centralized memory controller, which affects the inference speed and system frame rate of neural processing units.
Innovation Solution
A computing device with a system-on-chip (SoC) that groups master devices into logic device clusters based on operating requirements and assigns memory banks accordingly, using a stacked memory architecture with optimized network-on-chip (NoC) topology and connections between clusters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a centralized memory controller is used in conventional SoC, then memory access is simplified, but routing complexity increases and usable bandwidth decreases
Solution Approach 1:
The patent divides the centralized memory controller into distributed memory controllers located at each logic device cluster. Each cluster has its own memory controller that manages local memory banks, eliminating the single bottleneck of a centralized controller. This segmentation reduces routing complexity by localizing control functions while increasing usable bandwidth through parallel memory access paths.
Solution Approach 2:
The patent transitions from a two-dimensional planar interconnect architecture to a three-dimensional stacked architecture with memory layers positioned above logic layers. This dimensional change creates multiple interconnect pathways and increases spatial utilization, thereby increasing usable bandwidth without proportionally increasing routing complexity.
2Productivity
If the number of master devices in SoC increases, then processing capability improves, but routing complexity increases significantly
Solution Approach 1:
The patent groups master devices into logic device clusters, with each cluster containing one or more master devices and a local memory controller. This segmentation allows processing capability to scale by adding clusters while keeping each cluster's internal routing simple and manageable, preventing overall routing complexity from increasing significantly.
Solution Approach 2:
The patent combines master devices with memory controllers and memory banks into integrated logic device clusters. This merging reduces the number of independent interconnect nodes and simplifies routing by localizing data access within clusters, thereby enabling increased processing capability without proportional increases in routing complexity.
3Quantity of substance
If stacked memory is used above logic die, then bandwidth is increased, but data access latency must be optimized
Solution Approach 1:
The patent creates direct vertical interconnect pathways between logic device clusters in the logic layer and corresponding memory clusters in the memory layer. This segmentation of data paths into dedicated vertical channels increases bandwidth while minimizing latency by eliminating horizontal routing detours through intermediate interconnect nodes.
Data Source
AI summary
A computing device is provided. The computing device includes a system-on-chip (SoC) device, and the SoC device includes a plurality of master devices and a stacked memory. The master devices are arranged on a die. The master devices are grouped in space into a plurality of logic device clusters with a clustering scheme defined according to operating requirements of the master devices. The stacked memory is disposed above the die. Connections between the stacked memory and the plurality of logic device clusters are established according to the clustering scheme defined.