SOC Comparator Built-In Self-Test via Bit Pair Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Comparators in systems on a chip (SOCs) face challenges in reliable self-testing due to increasing complexity, making it difficult to detect errors and faults efficiently, especially in applications where safety and health considerations are critical, and existing Built-in Self Test (BIST) methods are cumbersome and time-consuming.
Innovation Solution
A built-in self-test device for SOC comparators that splits input signals into bit pairs, using a test controller to generate mismatches and verify expected output states, allowing for efficient operability testing by mismatching bit pairs one at a time, and includes a selection circuit to manage test signals and enable efficient fault detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing Built-in Self Test (BIST) methods are used for comparator testing, then fault detection capability is provided, but test time becomes excessively long and power consumption increases
Solution Approach 1:
The input signal is divided into N individual bit pairs, allowing the comparator to be tested in discrete, manageable units. The test controller applies mismatch signals to each bit pair sequentially rather than testing all bits simultaneously, which reduces the overall test time while maintaining comprehensive fault detection coverage for each bit position.
Solution Approach 2:
The test controller applies mismatch signals periodically to different bit pairs in a systematic sequence. By cycling through each bit pair and applying mismatch signals at regular intervals, the testing process achieves complete coverage efficiently, reducing total test time compared to exhaustive simultaneous testing while ensuring no fault is missed.
2Reliability
If comprehensive comparator testing is performed to ensure safety and health considerations, then reliability is improved, but power consumption increases
Solution Approach 1:
The testing process is segmented into discrete bit pair evaluations rather than activating all test circuits simultaneously. The test controller enables only the necessary test paths for each bit pair being evaluated, reducing overall power consumption while maintaining comprehensive safety verification through systematic coverage of all comparator inputs.
Solution Approach 2:
Power-intensive test signals are applied periodically to different bit pairs rather than continuously to all bits. This time-multiplexed approach ensures that at any given moment, only a subset of the comparator circuitry is actively being tested, significantly reducing peak and average power consumption while still achieving complete safety verification through systematic cycling through all bit positions.
3Adaptability or versatility
If increasing complexity is added to SOC comparators to enhance functionality, then versatility is improved, but ease of self-testing deteriorates
Solution Approach 1:
The test controller implements a universal testing approach that works regardless of the specific comparator configuration or bit width. By using a standardized mismatch signal application method that can accommodate any N-bit comparator, the system maintains ease of self-testing even as comparator versatility and functionality increase across different SOC applications.
Solution Approach 2:
The comparator performs self-testing through its own existing comparison functionality, without requiring external complex test equipment. The test controller leverages the comparator's natural operation by applying mismatch signals and evaluating the output, allowing the device to test itself autonomously. This self-service approach maintains ease of operation even as comparator complexity and versatility increase, because the testing mechanism scales naturally with the comparator design.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A device (300) for a system on a chip (SOC), the device includes: a comparator (306) that includes a first input port (306A), a second input port (306B), and an output port (306C). A first input signal and a second input signal are split into N bit pairs that include one bit from the first input signal and one bit from the second input signal. The comparator (306) is configured so a mismatch between the first input signal and the second input signal causes an output signal to assume a first expected state. The device (300) further comprises a test controller (310) to perform a first operability test by mismatching the N bit pairs and verifying that the output signal assumes the first expected state.