SoC In-System Component Testing for Runtime NPU Integrity
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Solution Overview
Problem
The integration of neural processing units (NPUs) in system-on-chip (SoC) or system-in-package (SiP) increases complexity, leading to higher defect rates during manufacturing, which can result in unpredictable AI operation failures due to minute defects that are not detected before shipment, posing risks in mission-critical applications like autonomous driving vehicles and AI robots.
Innovation Solution
A system-on-chip (SoC) with an in-system component tester (ICT) that monitors and tests functional components during runtime, allowing for the detection and isolation of defective components, and enabling reconfiguration using a field programmable gate array (FPGA) to replace or deactivate faulty components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple semiconductor components are integrated in SoC or SiP, then board space is reduced and manufacturing cost is lowered, but complexity is significantly increased leading to higher defect rates
Solution Approach 1:
The patent divides the SoC system into multiple functional components (NPU, GPU, CPU, memory, peripheral devices) that can be independently tested and managed. Each component can be individually monitored by the ICT, allowing defect isolation without affecting the entire system.
Solution Approach 2:
The patent introduces an In-System Component Tester (ICT) as an intermediary component that mediates between the system bus and functional components. The ICT monitors and tests components during runtime, detecting defects that were not found during manufacturing testing.
2Reliability
If manufacturing testing is performed before shipment, then most defects are detected, but minute defects are not found and are handed over to users
Solution Approach 1:
The patent performs preliminary testing during manufacturing, but also establishes continuous runtime testing as a preliminary protective measure before defects can cause system failure. The ICT proactively monitors components during operation to detect minute defects early.
Solution Approach 2:
The patent implements a feedback mechanism where the ICT continuously monitors functional components during runtime and provides real-time information about component status. This feedback loop allows detection of minute defects that develop after manufacturing testing.
3Volume of moving object
If NPU is integrated in SoC or SiP, then size of electronics is reduced, but complexity increases leading to unpredictable AI operation failures
Solution Approach 1:
The patent introduces the ICT as an intermediary that specifically monitors the NPU and other functional components for defects. This intermediary detection system helps ensure AI operation reliability by identifying defects that could cause unpredictable failures.
Solution Approach 2:
The patent uses status indicators (analogous to color changes) where the ICT can identify and flag defective components through distinct status signals, allowing operators to distinguish between healthy and defective NPUs in the integrated system.
Data Source
AI summary
A system on chip (SoC) for testing a component in a system during runtime includes a plurality of functional components; a system bus for allowing the plurality of functional components to communicate with each other; one or more wrappers, each connected to one of the plurality of functional components; and an in-system component tester (ICT). The ICT monitors, via the wrappers, states of the functional components; selects, as a component under test (CUT), at least one functional component in an idle state; tests, via the wrappers, the selected at least one functional component; interrupts the testing step with respect to the selected at least one functional component, based on a detection of a collision with an access from the system bus to the selected at least one functional component; and allows a connection of the at least one functional component to the system bus, based on the interrupting step.