Reduced Formal Model for SoC Connectivity Verification
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Solution Overview
Problem
The complexity of system-on-chip (SoC) designs leads to computationally intensive and time-consuming connectivity verification due to the state space explosion caused by millions of sequential logic elements, making it challenging to uncover all possible defects through formal verification.
Innovation Solution
A method that transforms the SoC design into a reduced formal model by selectively applying variable signals using multiplexers to verify connectivity between source and destination nodes, discarding irrelevant nodes and flip-flops, and using property identifiers to ensure efficient verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If formal verification is applied to exhaustively explore the mathematical representation of the SoC design, then all possible incorrect functions can be detected, but the state space explosion caused by design complexity makes the verification computationally intensive and time consuming
Solution Approach 1:
The patent segments the SoC design verification into multiple independent connectivity check modules, each verifying a specific connection between source and destination nodes. Instead of performing exhaustive formal verification on the entire SoC design simultaneously, the verification process is divided into smaller, manageable segments that can be processed independently and in parallel, significantly reducing the overall verification time while maintaining comprehensive defect detection coverage.
Solution Approach 2:
The patent extracts and removes irrelevant nodes and flip-flops from the netlist before performing connectivity verification. By identifying and eliminating portions of the design that are not relevant to the specific connectivity path being verified, the state space is dramatically reduced, allowing formal verification to complete much faster without sacrificing the ability to detect incorrect functions in the relevant pathways.
2Reliability
If formal verification is applied to exhaustively explore the mathematical representation of the SoC design, then all possible incorrect functions can be detected, but the state space explosion caused by design complexity makes the verification computationally intensive
Solution Approach 1:
The verification process is segmented into multiple independent connectivity check modules, each handling a specific source-destination node pair. This segmentation allows the computational workload to be distributed and processed in parallel, reducing the total energy consumption required for exhaustive verification of all possible incorrect functions in the SoC design.
Solution Approach 2:
Irrelevant nodes and flip-flops are extracted and removed from the netlist before verification. This extraction reduces the state space that needs to be explored during formal verification, thereby decreasing the computational energy consumption while maintaining the ability to detect all incorrect functions in the relevant connectivity paths.
3Reliability
If the entire SoC design is verified for connectivity, then all connections can be checked, but the complexity increases due to millions of sequential logic elements
Solution Approach 1:
The connectivity verification is segmented into multiple independent modules, each responsible for verifying a specific connection between source and destination nodes. Each module creates a simplified verification model containing only the relevant portion of the design, which reduces the complexity of individual verification tasks while maintaining comprehensive coverage of all connections through the modular approach.
Solution Approach 2:
The patent extracts and removes irrelevant nodes and flip-flops from the netlist before creating the verification model. This extraction process eliminates unnecessary complexity from millions of sequential logic elements, retaining only the essential components needed for connectivity verification, thereby reducing the overall verification model complexity while ensuring all connections are checked.
4Reliability
If simulation patterns are devised to uncover every possible defect in an SoC, then comprehensive defect detection can be achieved, but it may be challenging and time consuming
Solution Approach 1:
The verification process is segmented into standardized connectivity check modules that follow a uniform structure for creating verification models and performing connectivity analysis. This segmentation transforms the complex task of devising simulation patterns into a systematic, repeatable process that is easier to implement and maintain, while still achieving comprehensive defect detection through complete coverage of all source-destination node pairs.
Solution Approach 2:
The patent automatically extracts relevant nodes and flip-flops from the netlist based on the specific connectivity path being verified, eliminating the need for manual pattern development. This automated extraction process simplifies the verification process by removing the challenging task of manually devising simulation patterns while maintaining the ability to detect every possible defect through systematic connectivity checking.
Data Source
AI summary
A method of verifying connectivity in a circuit design, includes, in part, receiving a netlist of the circuit design; designating a plurality of destination nodes associated with the netlist; for each of the plurality of destination nodes, identifying one or more source nodes that are traversed from the destination node; for each source node identified as traversed from the destination node: transforming the netlist by including a first multiplexer having a first input terminal receiving a first variable logic value and an output terminal coupled to the source node; and enabling the first multiplexer to pass the first variable value to the destination node from the source node in order to check for connectivity between the source node and the destination node.