Constrained Metric Verification for SoC Parameter Space Analysis

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Solution Overview

Problem

Current integrated circuit (IC) design methods often lead to inefficient architectures due to the exploration of extreme parameter corners, resulting in overlooked design flaws and increased computational time in identifying performance issues, especially in system-on-a-chip (SoC) configurations where multiple parameters compete for resources.

Innovation Solution

A computer-implemented method and system that performs constrained analysis by selecting input parameters, simulating electronic device configurations, populating a database with simulation results, extracting distributions, finding correlations, and identifying expected output parameter values within a target range, using a regression coverage database and machine-learning techniques to efficiently explore the parameter space and predict performance impacts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If designers explore extreme parameter corners to evaluate performance, then performance optimization is improved, but design flaws are overlooked and computational time increases

Engineering Contradiction:
Improveperformance optimizationVSAvoiddesign flaw detection
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent transforms the verification approach from exploring extreme parameter corners to systematically varying parameters within realistic operating ranges. The constrained metric verification engine changes parameter exploration strategy by using statistical sampling and correlation analysis to identify design flaws without relying on extreme corner cases, thereby improving both reliability and reducing computational overhead.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces the traditional mechanical approach of exhaustive corner-case exploration with a statistical and computational methodology. By using constrained metric verification, correlation analysis, and machine learning techniques, the system substitutes brute-force parameter exploration with intelligent prediction models that identify critical design flaws more efficiently.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If exhaustive parameter space exploration is performed to find design flaws, then design reliability is improved, but computational time increases

Engineering Contradiction:
Improvedesign flaw detectionVSAvoidcomputational time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies partial action by performing verification on a constrained subset of parameter space rather than exhaustively exploring all possible combinations. The constrained metric verification engine focuses computational resources on identifying design flaws through statistical sampling and correlation analysis, achieving sufficient reliability without the excessive computational cost of complete enumeration.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent performs preliminary action by using machine learning models to predict performance outcomes and identify critical parameter combinations before conducting full verification. The constrained metric verification engine uses initial statistical analysis to guide subsequent detailed verification, reducing the overall computational time required for comprehensive design flaw detection.

Inventive Principle:
Principle #10Preliminary action

3Loss of information

If multiple input parameters are simulated to comprehensively analyze performance, then analysis completeness is improved, but computational complexity increases

Engineering Contradiction:
Improveparameter space coverageVSAvoidcomputational complexity
Core Design Contradiction:
Loss of informationVSDevice complexity

Solution Approach 1:

The patent extracts and focuses on the most critical input parameters that have the greatest impact on design flaws and performance. The constrained metric verification engine uses correlation analysis and machine learning to identify and prioritize key parameters, extracting only the essential information needed for comprehensive verification while eliminating redundant computational complexity from less significant parameters.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS10423741B1Constrained metric verification analysis of a system on chip
Publication Date: 2019.09.24 CADENCE DESIGN SYST INC
  • US10423741B1 patent drawing
  • US10423741B1 patent drawing
  • US10423741B1 patent drawing

AI summary

A method including selecting multiple input parameters of a device configuration environment to perform multiple simulations on an electronic device defined by the device configuration environment is provided. The method with multiple values for the multiple input parameters and a value of an output parameter resulting from the multiple simulations, and extracting a distribution of output parameter values and a distribution of input parameter values from a database. The method also includes finding a correlation involving the multiple input parameters and the output parameter based on a target range of the output parameter, and identifying an expected value of the output parameter using a range of values of the multiple input parameters in the correlation involving the multiple input parameters and the output parameter. A system and a nontransitory, computer-readable medium including instructions to perform the above method are also provided.