SOC Core Time Base Synchronization via Bit Subset Extraction

Solution Overview

Problem

Existing system-on-a-chip (SOC) designs face challenges in efficiently synchronizing multiple processing cores due to the lack of multiprocessor synchronization support, leading to increased on-die real-estate and power consumption from transmitting a full 64-bit time base counter to each core, and the need for multiple active clocks and phase lock loops.

Innovation Solution

Implementing an interrupt controller with a main time base counter and local counters, where only a subset of bits from the main counter is transmitted to synchronization logic blocks, which synchronize and decode the received bits to update local counters, allowing for different clock frequencies and operating voltages, reducing power consumption and on-die real-estate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a full 64-bit time base counter is provided to each processing core, then synchronization precision is improved, but on-die real-estate and power consumption increase

Engineering Contradiction:

Improvesynchronization precisionVSAvoidpower consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent extracts only the necessary subset of bits from the full 64-bit time base counter to be provided to each processing core. Instead of distributing the complete counter value, the system transmits only the most significant bits (e.g., upper 32 bits) that are sufficient for synchronization purposes, thereby reducing power consumption and on-die real-estate while maintaining adequate synchronization precision.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The time base counter is segmented into different bit portions, with only the relevant subset (e.g., upper bits) being transmitted to processing cores. The full counter is divided such that different portions serve different purposes: the transmitted subset provides synchronization information to cores, while the complete counter remains in the interrupt controller for system-wide timekeeping.

Inventive Principle:

Principle #1Segmentation

2Measurement precision

If a full 64-bit time base counter is provided to each processing core, then synchronization precision is improved, but on-die real-estate increases

Engineering Contradiction:

Improvesynchronization precisionVSAvoidon-die real-estate

Core Design Contradiction:

Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent extracts only the necessary subset of bits from the full 64-bit time base counter to be provided to each processing core. Instead of distributing the complete counter value, the system transmits only the most significant bits (e.g., upper 32 bits) that are sufficient for synchronization purposes, thereby reducing power consumption and on-die real-estate while maintaining adequate synchronization precision.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The time base counter is segmented into different bit portions, with only the relevant subset (e.g., upper bits) being transmitted to processing cores. The full counter is divided such that different portions serve different purposes: the transmitted subset provides synchronization information to cores, while the complete counter remains in the interrupt controller for system-wide timekeeping.

Inventive Principle:

Principle #1Segmentation

3Adaptability or versatility

If multiple active clocks and phase lock loops are used to support different frequencies, then adaptability is improved, but device complexity increases

Engineering Contradiction:

Improveclock frequency adaptabilityVSAvoidnumber of clocks and PLLs

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The interrupt controller serves multiple functions: it maintains the system-wide time base counter and simultaneously provides synchronization information to processing cores operating at different frequencies. The synchronization logic within each core is designed to handle frequency variations, making the system adaptable to different clock frequencies without requiring separate dedicated hardware for each frequency.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system allows processing cores to operate at different clock frequencies by changing the frequency parameter of individual cores while maintaining a single system-wide time base. The synchronization mechanism adapts to frequency changes by transmitting time base information that can be interpreted across different frequency domains, eliminating the need for multiple fixed-frequency clocks and PLLs.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS8977881B2Controller core time base synchronization

Publication Date: 2015.03.10 APPLE INC

AI summary

A system and method for efficiently synchronizing multiple processing cores on a system-on-a-chip (SOC). A SOC includes an interrupt controller and multiple processing cores. The interrupt controller includes a main time base counter. The SOC includes multiple local time base counters, each coupled to a respective one of the processing cores. Synchronization logic blocks are used to update the local counters. These blocks receive a subset of bits from the interrupt controller. The subset of bits represents a number of least significant bits of the main counter less than a total number of bits for the main counter. The logic blocks update an associated local counter according to changes to the received subset of bits. A difference may exist between values of the main counter in the interrupt controller and the local counter in the processing core. However, this difference may be a constant value.