SoC Co-Simulation With RISC-V Emulation for FPGA-Free Debugging
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Solution Overview
Problem
SoC designers face challenges in verifying and debugging complex designs due to the difficulty in distinguishing software and hardware errors, as existing debuggers and simulators lack comprehensive visibility and require access to an FPGA board, which is often unavailable early in the design phase.
Innovation Solution
A co-simulation framework that integrates a RISC-V processor emulator with an RTL simulator to simulate the entire SoC design, allowing for concurrent debugging of software and hardware without synthesis or FPGA board access, using TCP sockets for communication and AXI transfer protocol to mimic on-chip interactions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If on-chip debugging is used to monitor hardware signals, then hardware debugging capability is provided, but debugging time is extremely long and FPGA board access is required
Solution Approach 1:
The patent performs preliminary actions by implementing debug logic and instrumentation during the early design phases (HLS and RTL simulation) rather than waiting for FPGA implementation. This allows debugging capabilities to be built into the simulation environment itself, enabling early verification without requiring physical FPGA boards and significantly reducing overall debugging time.
2Ease of operation
If separate software debugger and hardware simulator are used, then software and hardware can be debugged independently, but integration and communication between them is difficult
Solution Approach 1:
The patent merges separate software debugging and hardware simulation capabilities into a unified co-simulation environment. The system integrates the software debugger (GDB), processor emulator, and hardware simulator with shared memory spaces and coordinated execution, allowing simultaneous debugging of both software and hardware components while maintaining their independence through virtualized interfaces and standardized communication protocols.
3Reliability
If FPGA board access is required for debugging, then real hardware verification is achieved, but accessibility is limited and board availability is required
Solution Approach 1:
The patent creates accurate virtual copies of the target hardware system through processor emulation and RTL simulation. These virtual models replicate the behavior, architecture, and interfaces of the actual FPGA-based system, enabling comprehensive debugging and verification in software without requiring physical FPGA board access. The virtual environment maintains sufficient fidelity to detect and diagnose real hardware issues.
4Loss of information
If comprehensive SoC verification is performed, then complete visibility into software and hardware is achieved, but debugging tool complexity increases
Solution Approach 1:
The patent implements a universal debugging platform that handles multiple debugging tasks through integrated tools. The co-simulation environment provides unified control over software debugging, hardware simulation, memory management, and signal monitoring through standardized interfaces and centralized coordination, reducing tool complexity while maintaining comprehensive verification capabilities across the entire SoC system.
Data Source
AI summary
A non-transitory computer readable medium is provided comprising instructions that when executed on a processor load a software program into a software debugger for execution on an emulated processor representing a processor portion of a system on chip (SoC), load a hardware design into a hardware simulator representing a programmable gate array portion of the SoC, coordinate execution of software debugger and hardware simulator to simulate operation of the SoC, communicate data between the software debugger and the hardware simulator, and display computed results and current values.