SoC CPU Debug Host Architecture for Internal Diagnostics

Solution Overview

Problem

Current debugging methods for computing systems, which involve external debuggers and interfaces, are costly and limit the extent of debugging capabilities, especially when dealing with CPU hang issues.

Innovation Solution

A System-on-Chip (SoC) architecture where multiple CPUs can operate as debug hosts, with event generation and control logic to initiate and perform debugging operations internally, selecting a debug target block and utilizing internal debugging code to diagnose issues without external intervention.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If an external debugger and external debug interface are used to perform debugging operations, then debugging capability is provided, but system cost increases and debugging functionality is limited

Engineering Contradiction:

Improvedebugging capabilityVSAvoidsystem cost

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The system enables CPUs to perform debugging operations autonomously without requiring external debuggers. The debug host CPU and debug target CPU work together internally to execute debugging code, access debug registers, and control debug target blocks, making the system self-sufficient for debugging purposes and eliminating the need for external debugging equipment

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The CPU is designed to serve dual purposes: normal computation tasks and debugging operations. By enabling the CPU to function as both a regular processor and a debug host, the system achieves multi-functionality, allowing the same hardware resource to perform multiple roles and reducing the need for dedicated external debugging equipment

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If an external debugger is connected through an external debug interface, then debugging operations can be performed, but the extent of debugging functions is limited

Engineering Contradiction:

Improvedebugging functionalityVSAvoiddebugging accessibility

Core Design Contradiction:

Adaptability or versatilityVSEase of operation

Solution Approach 1:

The system enables CPUs to perform debugging operations autonomously without requiring external debuggers. The debug host CPU and debug target CPU work together internally to execute debugging code, access debug registers, and control debug target blocks, making the system self-sufficient for debugging purposes and eliminating the need for external debugging equipment

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The debugging functionality is merged directly into the CPU architecture. The debug host CPU, debug target CPU, debugging code storage, and debug registers are integrated within the system, allowing debugging operations to be performed internally without external intervention. This merging expands debugging functionality beyond what external debuggers can provide

Inventive Principle:

Principle #5Merging (Combining)

3Productivity

If multiple CPUs are used in the system, then processing capability is improved, but debugging complexity increases when CPU hang occurs

Engineering Contradiction:

Improveprocessing capabilityVSAvoiddebugging complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

When a CPU hang is detected, another CPU acts as an intermediary debug host to investigate the hung CPU's state. The debug host CPU accesses the debug target CPU's registers and memory, effectively mediating the debugging process between the hung CPU and the debugging operations. This intermediary approach simplifies multi-CPU debugging by providing a dedicated debugging interface

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The system enables CPUs to perform debugging operations autonomously without requiring external debuggers. The debug host CPU and debug target CPU work together internally to execute debugging code, access debug registers, and control debug target blocks, making the system self-sufficient for debugging purposes and eliminating the need for external debugging equipment

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS10884056B2System-on-chip including CPU operating as debug host and method of operating the same

Publication Date: 2021.01.05 SAMSUNG ELECTRONICS CO LTD

AI summary

Provided is a method of operating a system-on-chip (SoC) including a plurality of CPUs. The method includes: receiving a debug request by a first CPU of the CPUs; outputting a first signal to the CPUs by the first CPU in response to the debug request; selecting a second CPU from the CPUs to control the debugging based on the first signal; and performing a debug operation by selecting a debug target block by the second CPU.