SOC Current Profile Modeling for IVR Co-Design and Power Integrity
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Solution Overview
Problem
Current integrated voltage regulator (IVR) strategies for Systems on Chip (SOCs) face challenges such as increased space usage on the SOC package, potential blocking of SOC signals, and inefficiencies in power delivery and dynamic voltage and frequency scaling (DVFS).
Innovation Solution
The integration of an IVR with an SOC to reduce system size, improve power delivery efficiency, and enhance dynamic voltage and frequency scaling, while also customizing the IVR for the SOC through early co-simulation stages to avoid underdesign and overdesign risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If an integrated voltage regulator (IVR) is integrated with an SOC, then power delivery efficiency and dynamic voltage and frequency scaling are improved, but space usage on the SOC package increases and SOC signals may be blocked
Solution Approach 1:
The patent merges the IVR and SOC into a single integrated unit, combining the voltage regulator functionality directly with the system on chip. This integration eliminates the need for separate IVR components and interconnects, thereby improving power delivery efficiency while managing space through unified architecture design
Solution Approach 2:
The patent employs three-dimensional stacking architecture where the IVR is positioned in a different spatial layer relative to the SOC. This vertical integration approach allows compact co-location of components, improving power delivery efficiency while minimizing the footprint and avoiding signal blocking on the package surface
2Power
If an IVR is integrated with an SOC, then power delivery efficiency is improved, but SOC signals may be blocked
Solution Approach 1:
The patent positions the IVR in a vertical layer above or below the SOC, utilizing the z-dimension for component placement. This spatial separation in the vertical direction enables efficient power delivery through direct integration while preventing signal blocking, as the IVR components do not occupy the same planar space as the SOC signal paths
Solution Approach 2:
The patent segments the integrated structure into distinct functional layers, separating the power delivery functions (IVR) from the signal processing functions (SOC). This layering strategy allows independent optimization of each subsystem while maintaining efficient power delivery and preventing signal interference through physical separation in the vertical dimension
3Reliability
If co-simulation is performed in early design stages, then underdesign and overdesign risks are avoided, but turnaround time for co-design increases
Solution Approach 1:
The patent performs co-simulation of the IVR and SOC during early design stages, before final implementation. This preliminary simulation allows designers to identify and correct potential underdesign or overdesign issues early in the development process, improving design accuracy while enabling parallel development activities that can mitigate time delays
4Adaptability or versatility
If IVR and SOC are designed separately, then design flexibility is maintained, but power integrity and efficiency are compromised
Solution Approach 1:
The patent integrates the IVR and SOC into a unified design framework, merging previously separate design processes into a coordinated system-level approach. This integration maintains design flexibility through modular architecture while improving power integrity by optimizing the power delivery network specifically for the integrated structure, enabling better power efficiency than separate designs could achieve
Data Source
AI summary
A method includes: extracting a first current profile model corresponding to a System on Chip (SOC) at a first design stage of the SOC; determining that a first design data of an Integrated Voltage Regulator (IVR) and the SOC pass a first co-simulation based on the extracted first current profile model; extracting a second current profile model corresponding to the SOC at a second design stage of the SOC, the second design stage being subsequent to the first design stage; refining the first design data of the IVR to generate a second design data of the IVR; determining that the second design data of the IVR and the SOC pass a second co-simulation based on the extracted second current profile model.