SoC Data Detection Circuit for Fault State Verification
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Solution Overview
Problem
Current data verification methods in system-on-chip designs require hardware-based error correction, leading to increased space occupation and power consumption, which is inefficient and not suitable for timely and accurate detection of faults in memory and register configurations.
Innovation Solution
A circuit detection method that periodically reads data from storage areas using a preset calculation method to determine fault states without additional hardware, allowing for timely and accurate detection while reducing power consumption and space occupation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware-based error correction methods (ECC and Parity) are used to verify data in memories and registers, then data integrity is ensured, but the system occupies more space and consumes more power
Solution Approach 1:
The patent extracts the data verification function from dedicated hardware circuits (ECC/Parity units) and relocates it to software execution. The processor periodically reads stored data and performs verification calculations using general-purpose computing resources, thereby removing specialized verification hardware from the system while maintaining data integrity checking capabilities
Solution Approach 2:
The patent makes the processor universal by using it for both data processing and data verification tasks. Instead of having separate dedicated hardware for verification, the same processor that executes application code also performs error detection and correction calculations, thereby eliminating the need for additional verification-specific hardware components
2Reliability
If hardware-based error correction methods (ECC and Parity) are used to verify data in memories and registers, then data integrity is ensured, but the system consumes more power
Solution Approach 1:
The patent extracts the continuous power-consuming verification hardware circuits from the system and replaces them with periodic software-based verification. By moving verification to software, the system only consumes verification-related power when actually performing checks, rather than continuously powering dedicated verification hardware, thereby significantly reducing overall power consumption while maintaining data integrity
Solution Approach 2:
The patent implements periodic verification where the processor checks data integrity at predetermined time intervals rather than continuously. This periodic approach allows the system to enter low-power states between verification cycles, reducing average power consumption while still ensuring data integrity through regular checking
3Difficulty of detecting and measuring
If additional hardware is added for data verification, then verification capability is improved, but the system complexity increases
Solution Approach 1:
The patent extracts the verification capability requirement from hardware implementation and fulfills it through software. By removing dedicated verification hardware circuits (ECC units, Parity generators) and implementing verification logic in software, the system maintains full verification capability while significantly reducing hardware complexity and making the system easier to design and modify
Data Source
AI summary
Embodiments of the present disclosure disclose a circuit detection method and a data detection circuit. The circuit detection method comprises: if a current time point reaches a preset detection time period, based on a data storage address of a detected module, reading a data to be detected corresponding to the detected module from a storage area corresponding to the data storage address; using a preset calculation method corresponding to the detected module to perform a calculation on the data to be detected to obtain a first calculation result; based on the first calculation result and a preset calculation result corresponding to the data storage address, determining a fault state of the detected module. The embodiments of the present disclosure can detect the storage circuit in a timely and accurate manner without data verification by adding hardware, thereby saving space occupied by the system and reducing power consumption.