Automated Data Transfer Network Generation for SOC Hardware Accelerators
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Solution Overview
Problem
The process of incorporating hardware accelerators into System-On-A-Chip (SOC) designs is time-consuming and prone to errors due to the manual and labor-intensive nature of data transfer network creation between hardware accelerators and microprocessors.
Innovation Solution
An automated method for determining, characterizing, and correlating data transfers within a SOC, generating a programmatic description of a data transfer network that connects hardware accelerators and microprocessors, utilizing a processor and CAD tools to parse high-level programming language circuit designs and allocate resources for optimized data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual process is used to incorporate hardware accelerators into SOC designs, then flexibility and control are maintained, but the process becomes time-consuming and error-prone
Solution Approach 1:
The system enables self-service by automatically generating the data transfer network configuration based on the hardware accelerator description and SOC architecture specifications. The tool independently performs resource allocation, data transfer path generation, and configuration file creation without requiring manual intervention, thus reducing both time and errors while maintaining design control through automated verification against specifications.
Solution Approach 2:
The manual mechanical process of integrating hardware accelerators is replaced by an automated software system that parses hardware accelerator descriptions, analyzes data transfer requirements, and generates configuration files. This substitution eliminates human error in manual configuration while significantly reducing integration time through algorithmic processing of the design specifications.
2Productivity
If automated method is used to generate data transfer network, then productivity and error reduction are achieved, but system complexity increases
Solution Approach 1:
The automation system is segmented into distinct functional modules: hardware accelerator description parser, data transfer requirement analyzer, resource allocation engine, and configuration file generator. Each module handles a specific aspect of the integration process, making the overall complex system manageable through clear separation of concerns while maintaining high productivity through coordinated automated operation.
Solution Approach 2:
The system introduces an intermediary automated tool that acts as a mediator between the hardware accelerator design specifications and the SOC configuration requirements. This intermediary automatically translates high-level hardware descriptions into detailed data transfer network configurations, managing the complexity by providing a standardized interface between design intent and implementation details.
3Manufacturing precision
If comprehensive characterization and correlation of data transfers is performed, then data transfer network accuracy is improved, but processing time increases
Solution Approach 1:
The system performs preliminary action by automatically characterizing and correlating all data transfer requirements during the initial design phase. The automated tool analyzes hardware accelerator descriptions to identify all data transfer paths, bandwidth requirements, and timing constraints before generation of the configuration, ensuring high accuracy in the data transfer network setup while reducing later iteration time through comprehensive upfront analysis.
Data Source
AI summary
A method of automatically developing a data transfer network includes determining, using a processor, a plurality of data transfers of a function of a circuit design marked for hardware acceleration within a target integrated circuit. The circuit design is specified in a high level programming language, and at least one other function of the circuit design remains executable by a microprocessor of the target integrated circuit. Each of the plurality of data transfers is characterized. Each of the plurality of data transfers is correlated with resources of the target integrated circuit. A programmatic description of a data transfer network is generated for the circuit design. The data transfer network connects the hardware accelerator and the microprocessor according to the characterizing and the correlating.