SoC Deadlock Controller Isolating Processor State
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Solution Overview
Problem
System-on-chip (SoC) components often enter a deadlock state, making it difficult to analyze and debug due to the inability to receive responses, leading to inoperable processor states and lost state information when attempting to reset the system.
Innovation Solution
Incorporating a deadlock controller with a debugging path bus and isolation cell to detect deadlock states, isolate the processor, extract state information, and reset the main bus while preserving the processor's state, allowing for effective debugging of the deadlock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the system attempts to reset the processor in a deadlock state, then the system can be restored to operational state, but the processor state information is lost making debugging difficult
Solution Approach 1:
The patent applies preliminary action by extracting and preserving processor state information before resetting the processor. The deadlock controller detects the deadlock state and captures the processor state (registers, memory contents, instruction pointers) before the reset operation occurs, ensuring the information is available for subsequent debugging analysis.
Solution Approach 2:
The patent implements copying by creating a duplicate copy of the processor state information and storing it in a separate storage location controlled by the deadlock controller. This copy preserves the deadlock state data independently from the processor reset, allowing debugging without losing the original state information.
2Loss of information
If the processor is isolated from the main bus using an isolation cell, then state information can be preserved during reset, but the device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the bus system into two separate paths: the main bus for normal operation and the debugging path bus for state extraction. The isolation cell acts as a segmentation point that can connect or disconnect the processor from the main bus, allowing independent control of normal operation and debugging functions.
Solution Approach 2:
The patent uses an isolation cell as an intermediary component between the processor and the main bus. This intermediary can switch the processor's connection state, enabling it to be isolated during debugging operations while maintaining normal bus connectivity during regular operation, thus managing complexity through controlled mediation.
3Difficulty of detecting and measuring
If a deadlock controller is added to detect and manage deadlock states, then debugging capability is improved, but the device complexity increases
Solution Approach 1:
The deadlock controller is designed with multi-functionality, serving both as a deadlock detection mechanism and as a state extraction controller. It monitors bus transactions to detect deadlocks and simultaneously manages the isolation cell and state information extraction through its control outputs, reducing overall system complexity by consolidating functions.
Solution Approach 2:
The patent merges the deadlock detection function and the state extraction control function into a single deadlock controller unit. This consolidation integrates multiple responsibilities (detection, isolation control, state extraction initiation) into one component, simplifying the overall system architecture compared to having separate dedicated components for each function.
Data Source
AI summary
A system-on-chip (SoC) to perform a deadlock control on a processor of the SoC, the SoC including the processor including a plurality of central processing unit (CPU) cores, a first bus connected to the processor, a graphic processing unit (GPU) connected to the first bus, a memory controller connected to the first bus, a second bus connected to the processor, an isolation cell including a logic circuit configured to retain a signal value input to the processor according to an isolation signal, and a deadlock controller connected to the first bus and the second bus. The deadlock controller is configured to isolate the processor, which is in a deadlock state, from the first bus by applying the isolation signal on the isolation cell, and to extract, via the second bus, state information of the isolated processor in the deadlock state.