Debug Logic Circuit for SoC Power Sequencing FSMs
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Solution Overview
Problem
Debugging finite state machines (FSMs) that sequence System-On-Chips (SoCs) through lowest power states is challenging due to the need for debug logic circuitry on Always On (AO) power rails, which increases area and leakage power, and existing debug logic fails to provide sufficient visibility for complex power sequencing FSMs.
Innovation Solution
Implementing a debug logic circuit connected to a SOC voltage source and masking output signals to prevent the debug logic circuit from entering low power or reset states, allowing it to remain powered up and debug the FSMs while they transition through lowest power states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If debug logic circuitry is added to AO rails to debug power sequencing FSMs, then debugging capability is improved, but area increases which increases leakage power
Solution Approach 1:
The patent introduces an intermediary power domain configuration where the debug logic circuit is placed in a separate debug power domain that remains powered during lowest power states, while the main SOC power domains are turned off. This intermediary domain acts as a mediator that allows debugging without requiring debug logic to be integrated into the always-on domain, thus minimizing area overhead and leakage power while maintaining full debugging capability.
2Area of stationary object
If simple logic is added to AO rails for debugging, then area overhead is reduced, but debugging visibility is insufficient for complex power sequencing FSMs
Solution Approach 1:
The patent segments the power domain structure into multiple independent domains: main power domains that can be fully powered off, an always-on domain for essential functions, and a separate debug power domain for debugging logic. This segmentation allows the debug logic to have full visibility and control over complex power sequencing FSMs without requiring minimal area overhead on the AO rails, as each domain can be independently configured and powered.
3Loss of energy
If all power rails except AO rails are turned OFF in lowest power state, then power consumption is minimized, but debug logic cannot remain powered up to debug FSMs
Solution Approach 1:
The patent creates an intermediary debug power domain that serves as a bridge between the powered-off main domains and the always-on domain. This intermediary domain remains powered during lowest power states specifically to support debugging operations, while the main power domains are fully turned off to minimize power consumption. The intermediary domain allows debug logic to monitor and control FSM operations without preventing the system from achieving minimal power consumption state.
Data Source
AI summary
Methods and apparatus for debugging finite state machine are disclosed. The method includes implementing a debug logic circuit and connecting the debug logic circuit to a system on chip (SoC) voltage source. The method includes operating a finite state machine that sequences the SoC from a low power state to a next low power state and generating respective output signals corresponding to the low power states and wherein the finite state machine is connected to Always On voltage source. The method includes masking the output signals to generate respective masked output signals, and applying the masked output signals to SoC circuit elements to prevent from transitioning into low power states and hence keeping the debug logic circuitry alive. The method includes debugging the finite state machine in the lowest power state by the debug logic circuit.