SoC Debugging via Intermediate Result Capture for AI Accelerators
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Solution Overview
Problem
The debugging efficiency of AI accelerators and other components on system on chip is low due to the large amounts of data flow, with no mechanism to obtain intermediate debugging results, making post-processing output data necessary for debugging.
Innovation Solution
Implementing breakpoint, step-in, step-out, jump, and pause features for logic functions on components to be debugged, mimicking software debugging capabilities with trace buffers, allowing the global control logic to pause after each tile and store results for review.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If deep neural networks with multiple layers are used to improve accuracy, then computing capability is improved, but debugging difficulty increases due to large amounts of data flow through multiple modules
Solution Approach 1:
The patent segments the data flow into multiple channels, each carrying different types of information (input data, intermediate results, control signals). This segmentation allows the debugging system to selectively monitor and analyze specific data streams without being overwhelmed by the total data volume, thus reducing debugging difficulty while maintaining the deep network architecture for computing power.
Solution Approach 2:
The patent introduces a debugging system as an intermediary between the deep neural network modules. This intermediary captures, stores, and retrieves intermediate calculation results at various stages of the network, enabling researchers to inspect data flow without disrupting the computing process. The intermediary acts as a buffer that decouples the debugging function from the computing function.
2Power
If more layers are added to CNNs to improve accuracy, then processing capability is improved, but intermediate result storage requirements increase
Solution Approach 1:
The patent extracts intermediate calculation results from the main data flow and stores them in dedicated storage units within the debugging system. By taking out these intermediate results, the system can retain them for later analysis without requiring additional storage capacity within the neural network modules themselves, thus maintaining processing capability while managing storage requirements.
Solution Approach 2:
The patent moves intermediate result storage from the spatial dimension (within-chip memory) to the temporal dimension (external storage system). Intermediate results are captured and stored externally, allowing the neural network to continue processing without being constrained by on-chip memory capacity. This dimensional shift enables deeper networks without proportionally increasing storage requirements.
3Reliability
If post silicon debugging is performed on AI accelerators, then bug detection is possible, but debugging efficiency is very low due to lack of intermediate result access
Solution Approach 1:
The patent implements preliminary action by pre-configuring the debugging system with storage units and capture mechanisms before the AI accelerator operates. Intermediate results are automatically captured and stored as they are generated during normal operation, eliminating the need for complex post-processing analysis. This preliminary setup enables efficient bug detection by making intermediate data readily accessible.
Solution Approach 2:
The patent establishes a feedback mechanism where intermediate calculation results are continuously monitored, stored, and made available for analysis. This feedback loop allows researchers to immediately observe the effects of bugs on intermediate data, enabling rapid identification and correction of issues. The feedback system transforms debugging from a slow post-silicon process to an interactive real-time activity.
Data Source
AI summary
Provided are a method and an apparatus for debugging, and a system on chip. The method for debugging includes: a component to be debugged receives a debugging instruction from a controller, and the component to be debugged performs debugging operation according to the debugging instruction and configuration of a state machine inside the component to be debugged. Then an SW level debugging operation of component on system on chip can be achieved, which improves the debugging efficiency of these components with large amounts of data flow on system on chip.