On-Chip Debug Architecture for SoC Power Management
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Solution Overview
Problem
Debugging of System-on-Chip (SoC) devices is hindered by the integration of multiple core devices onto a single chip, which reduces access for external debugging tools due to internal data transfer and increased complexity, leading to high costs for debug units and ports, and incomplete system-level debugging capabilities.
Innovation Solution
A method of powering down a portion of an integrated circuit chip, extracting and storing configuration information from debug units, and restoring it upon power-up to ensure seamless debugging sessions, utilizing a shared hub for efficient data routing and storage, and implementing a hierarchical debug architecture for comprehensive system debugging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple core devices are integrated onto a single chip to reduce product size, then product size is reduced, but access for external debugging tools is reduced
Solution Approach 1:
The patent introduces an on-chip debug unit as an intermediary component that bridges the gap between the integrated core devices and external debugging tools. This debug unit provides interfaces and control logic that allow external tools to access and control the integrated cores without requiring direct physical access to internal chip connections, thus resolving the contradiction between compact integration and debugging accessibility.
Solution Approach 2:
The debug unit is designed with multi-functional capabilities, serving as a universal interface for multiple core devices simultaneously. It can control and monitor different types of cores (RISC, CISC, DSP, etc.) through standardized interfaces, eliminating the need for separate debugging access for each core and reducing overall product size while maintaining comprehensive debugging capability.
2Reliability
If debug units are provided for each core device to enable independent debugging, then debugging capability is improved, but silicon area cost increases
Solution Approach 1:
The patent merges multiple individual debug units into a single shared on-chip debug unit that can service multiple core devices. This consolidated debug unit incorporates multiple interfaces and control logic that can be dynamically allocated to different cores, reducing the total silicon area required while maintaining the ability to independently debug each core device.
Solution Approach 2:
The shared debug unit is designed with universal functionality to interface with multiple types of core devices simultaneously. It contains configurable interfaces and control mechanisms that can be adapted to work with different core architectures, providing comprehensive debugging capability across multiple cores without requiring dedicated debug units for each core, thus reducing silicon area cost.
3Use of energy by moving object
If configuration information is not preserved during power down, then power consumption is reduced, but debugging sessions are interrupted
Solution Approach 1:
The patent implements preliminary action by saving the debug unit's configuration information to non-volatile memory before the chip is powered down. This ensures that when power is restored, the configuration data is already available, allowing the debugging session to resume immediately without interruption or data loss, thus resolving the contradiction between power savings and session continuity.
4Productivity
If internal data transfer is increased to support multiple cores, then processing capability is improved, but debugging access is reduced
Solution Approach 1:
The on-chip debug unit acts as an intermediary layer that simplifies access to the complex internal data transfer pathways of multi-core systems. It provides standardized interfaces and control mechanisms that allow external debugging tools to monitor and control internal data flow without requiring direct access to the complex internal bus structures, thus maintaining high processing capability while improving debugging accessibility.
Data Source
AI summary
Roughly described, a method of powering down a portion of an integrated circuit chip, the portion of the integrated circuit chip comprising a plurality of peripheral circuits, each peripheral circuit being connected to a respective debug unit, the method comprising: prior to power down, extracting from each debug unit configuration information of that debug unit; storing the configuration information of the debug units in a memory on the integrated circuit chip during power down of the portion of the integrated circuit chip; and on power up, restoring the configuration information of each debug unit to that debug unit prior resuming operation of that debug unit and the peripheral circuit connected to that debug unit.