SoC Fault Detection via Debug Trace Comparison
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Solution Overview
Problem
Some processor architectures, particularly those with out-of-order instruction execution and superscalar designs, make it impractical to implement redundant processors for lockstep execution due to the need for replication of execution units and voting circuits, hindering effective functional safety monitoring.
Innovation Solution
The use of embedded trace hardware in a programmable logic subsystem to non-intrusively monitor processors through a debug interface, comparing trace data from one or more processors to detect discrepancies and generate error signals, ensuring functional safety without the need for redundant processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant processors are implemented for lockstep execution to ensure functional safety, then reliability is improved, but device complexity increases due to replication of execution units and voting circuits
Solution Approach 1:
The patent creates a virtual copy of the processor execution trace through debug interface circuitry rather than physically replicating the entire processor. The trace data captured via debug interfaces (ETM, DTM, JTAG) represents a copy of the processor's execution state, which is then fed to a safety processor for comparison and safety determination, avoiding the need for complete processor replication
Solution Approach 2:
The patent introduces debug interface circuitry and trace data as an intermediary between the main processor and the safety monitoring function. Instead of directly comparing outputs from two full processors, the system uses trace data captured through debug interfaces as a mediator to convey processor state information to the safety processor, simplifying the architecture while maintaining safety monitoring capability
2Measurement precision
If trace data is transmitted continuously from the processor to the fault detection circuit, then measurement precision is improved for fault detection, but loss of time occurs due to data transmission and processing delays
Solution Approach 1:
The safety processor pre-processes and compares trace data as it arrives from the debug interface, maintaining a rolling comparison window rather than waiting to collect complete data sets. This preliminary action allows the system to detect discrepancies earlier in the execution sequence, reducing the time delay between fault occurrence and detection while maintaining detection precision
Solution Approach 2:
The system implements asynchronous processing where the safety processor can independently analyze trace data at its own pace without being synchronized to the main processor's clock cycle. When discrepancies are detected, the safety processor immediately generates safety signals, skipping unnecessary waiting periods and rushing through the critical detection and response phases to minimize time loss
Data Source
AI summary
Disclosed approaches involve at least one processor executing a program and a debug interface circuit coupled to the processor. The debug interface circuit is configured to transmit first trace data from the first processor. A debug access port is coupled to the debug interface circuit. A fault detection circuit is coupled to the debug access port and is configured to receive the first trace data via the debug access port and compare the first trace data to second data. The fault detection circuit generates an error signal to the first processor in response to a discrepancy between the first trace data and the second data.