SoC Hardware Decoder Wake-Up for Low-Power Bus Signal Processing
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Solution Overview
Problem
In environmental monitoring systems, particularly in IoT nodes like smoke detectors connected via two-wire fire buses, there is a challenge in reducing energy consumption and processing capability requirements as the number of nodes increases, necessitating a more efficient method to manage signal processing without overburdening the microprocessor core.
Innovation Solution
A system-on-chip design incorporating a hardware decoder that decodes signal frames from an external bus, wakes up the microprocessor core only when necessary, and allows it to remain in a sleep state until a wake-up command is received, thereby reducing energy consumption and processing demands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the microprocessor core continuously monitors the GPIO port to decode signals, then the system can respond to bus signals in real time, but the energy consumption increases and processing capability requirements rise
Solution Approach 1:
The patent divides the signal processing function into two parts: the hardware decoder handles signal reception and address matching, while the microprocessor core only processes commands when addressed. This segmentation allows the microprocessor to sleep during idle periods while maintaining real-time responsiveness through the always-on hardware decoder.
Solution Approach 2:
The hardware decoder acts as an intermediary between the external bus and the microprocessor core. It filters incoming signals and only wakes up the microprocessor when a signal is intended for it, reducing the microprocessor's active monitoring burden while ensuring real-time response to relevant signals.
2Ease of manufacture
If the microprocessor core continuously monitors and decodes signals, then processing capability is sufficient, but low specification components cannot be used and system cost increases
Solution Approach 1:
The patent extracts the signal decoding function from the microprocessor core and implements it in dedicated hardware. This allows the use of low-specification, low-cost microprocessor cores while maintaining full decoding capability through the separate hardware decoder module.
Solution Approach 2:
The patent replaces the software-based signal monitoring and decoding mechanism (which requires high-processing-capability microprocessors) with a hardware-based decoding mechanism. This substitution enables the use of simpler, lower-cost microprocessor components.
3Loss of time
If the microprocessor core remains active to handle signals promptly, then response time is reduced, but energy consumption increases
Solution Approach 1:
The patent implements periodic action by having the microprocessor alternate between sleep mode and active mode. The hardware decoder continuously monitors the bus (periodic action), and only wakes up the microprocessor when necessary, achieving energy efficiency without sacrificing response time for addressed signals.
Data Source
AI summary
A system-on-chip in accordance with an aspect of the present application comprises: a communication interface connected with an external bus; a hardware decoder connected with the communication interface; and a microprocessor core connected with the communication interface and the hardware decoder, wherein the hardware decoder is configured to receive, via the communication interface, a signal frame transmitted on the external bus, to extract a receiver address from the signal frame as received and to send a wake-up command to the microprocessor core upon determining that a receiver of the signal frame is the system-on-chip, wherein the microprocessor core is configured to remain in a sleep mode until the wake-up command is received, and to perform an operation specified by a control command contained in the signal frame in response to the wake-up command.