SoC Delay Test Device Isolating Units for Precision Measurement
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional test apparatuses face difficulties in detecting critical paths causing signal delay in system-on-chip due to variations in manufacturing processes, especially at higher operating frequencies, as they perform delay tests on paths used for original functions, making it hard to isolate and measure propagation times accurately.
Innovation Solution
A test device for system-on-chip incorporating a sequential logic circuit and a test circuit with separate delay units, including CMOS, PMOS, and NMOS transistors, that converts serial input signals to parallel and back to serial formats, performs delay tests using system and test clock signals, and provides output signals representing delay test results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional test apparatus performs delay test on paths used for original functions, then test coverage is achieved, but measurement precision deteriorates due to inability to isolate delay units
Solution Approach 1:
The test device segments the test circuit into separate delay units that are independent from the logic circuit performing original functions. Each delay unit can be individually tested for propagation time, allowing precise measurement without interference from other circuit elements. The segmentation enables isolated testing of each path component.
Solution Approach 2:
The delay units are extracted from the logic circuit and placed as separate, dedicated test structures. This extraction allows the delay units to be specifically optimized for timing measurement without being constrained by the functional requirements of the main logic circuit, thereby improving measurement precision.
2Speed
If operating frequency of system-on-chip increases, then processing speed improves, but signal delay becomes more significant and harder to detect
Solution Approach 1:
The test device replaces complex functional logic operations with simple delay unit operations that merely measure signal propagation time. By substituting functional circuitry with dedicated timing measurement structures, the device can accurately detect signal delays even at high operating frequencies where functional testing becomes unreliable.
3Measurement precision
If separate delay units are introduced for testing, then measurement precision improves, but device complexity increases
Solution Approach 1:
The delay units are designed to serve multiple purposes: they can be used for both functional testing and precise propagation time measurement. The same delay unit structure supports different test modes and can be integrated into various test scenarios, reducing the need for entirely separate testing infrastructure.
Data Source
AI summary
A test device for a system-on-chip includes a sequential logic circuit and a test circuit. The sequential logic circuit generates a test input signal by converting a serial input signal into a parallel format in response to a serial clock signal and a serial enable signal and generates a serial output signal by converting a test output signal into a serial format in response to the serial clock signal and the serial enable signal. The test circuit includes at least one delay unit that is separated from a logic circuit performing original functions of the system-on-chip, performs a delay test on the at least one delay unit using the test input signal in response to a system clock signal and a test enable signal, and provides the test output signal to the sequential logic circuit, where the test output signal representing a result of the delay test.