SoC Die Package Exposed Top Surface for Heat Dissipation
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Solution Overview
Problem
Semiconductor device packages face increased operating temperatures due to reduced heat dissipation from encapsulation layers, leading to thermal throttling and premature failure, as well as structural issues from coefficient of thermal expansion mismatches causing warpage and cracking.
Innovation Solution
A semiconductor device package design where the SoC die package is positioned above the memory die package, with an exposed top surface for enhanced heat dissipation and a structural enhancement layer to mitigate thermal expansion mismatches, including a grinding process to expose the SoC die package through the encapsulation layer and applying a heatsink, and using a die attach film and structural enhancement layer for increased robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an encapsulation layer is used to protect semiconductor die packages, then reliability is improved, but heat dissipation is reduced causing increased operating temperatures
Solution Approach 1:
The encapsulation structure is segmented into two distinct parts: a first encapsulation layer that provides protection, and a second encapsulation layer with higher thermal conductivity that provides heat dissipation. This segmentation allows each layer to specialize in one function, resolving the contradiction between protection and heat dissipation.
Solution Approach 2:
The patent uses composite encapsulation structures combining materials with different properties. The first encapsulation layer uses standard protective materials, while the second encapsulation layer uses materials with higher thermal conductivity (such as metal-filled epoxies or ceramic composites) to enable effective heat dissipation while maintaining protection.
2Reliability
If encapsulation layers are used to protect semiconductor die packages, then reliability is improved, but structural integrity deteriorates due to thermal expansion mismatches causing warpage and cracking
Solution Approach 1:
The patent modifies the thermal expansion parameters of the encapsulation layers by selecting materials and compositions with thermal expansion coefficients matched to the semiconductor die packages. This parameter matching reduces thermal stress during temperature cycling, preventing warpage and cracking while maintaining protective function.
Solution Approach 2:
The encapsulation layers act as intermediary structures that buffer and accommodate thermal expansion differences between the semiconductor die packages and the substrate. The layered encapsulation structure with different thermal properties serves as a transition zone that mediates the thermal stress, preventing direct transmission of expansion mismatches that would cause structural failure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces operating temperatures, increases the lifespan of the SoC die package, and enhances structural integrity by improving thermal dissipation and reducing the likelihood of physical damage from thermal stress.
Implementation Method 1
a heatsink... for enhanced heat dissipation
Implementation Method 2
coefficient of thermal expansion mismatches causing warpage and cracking
Data Source
AI summary
A system on chip (SoC) die package is attached to a redistribution structure of a semiconductor device package such that a top surface of the SoC die package is above a top surface of an adjacent memory die package. This may be achieved through the use of various attachment structures that increase the height of the SoC die package. After encapsulating the memory die package and the SoC die package in an encapsulation layer, the encapsulation layer is grinded down. The top surface of the SoC die package being above the top surface of the adjacent memory die package results in the top surface of the SoC die package being exposed through the encapsulation layer after the grinding operation. This enables heat to be dissipated through the top surface of the SoC die package.