Low-Power SoC-to-Display-Driver Synchronization With Clock Switching

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Solution Overview

Problem

OLED display devices face challenges with high production costs and large power consumption, particularly in low power applications where reducing power consumption is crucial for extending battery durability.

Innovation Solution

A synchronization method and electronic device design that allows the display controller to be fully powered off when power consumption is reduced, using an additional clock signal to maintain synchronization with the display driver integrated circuit, and employing a multiplexer to switch between synchronization and clock signals based on power consumption needs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the display controller continuously provides synchronization signals to maintain synchronization with the display driver integrated circuit, then synchronization reliability is improved, but power consumption increases

Engineering Contradiction:
Improvesynchronization reliabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The display controller operates in periodic intervals, alternating between active mode (providing synchronization signals) and sleep mode (power off). The controller determines whether the displayed content has changed, and only activates to provide synchronization signals when changes occur, otherwise it remains powered off. This periodic operation dramatically reduces power consumption while maintaining necessary synchronization.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent extracts the essential synchronization function from the continuous operation requirement. By using a change detection mechanism, the system identifies only when synchronization signals are actually needed (when content changes), and separates this from continuous signal provision. The controller can be fully powered off when no changes occur, extracting only the necessary moments of active operation.

Inventive Principle:
Principle #2Taking out (Extraction)

2Use of energy by moving object

If the display controller is fully powered off to reduce power consumption, then power consumption is reduced, but synchronization with the display driver integrated circuit is lost

Engineering Contradiction:
Improvepower consumptionVSAvoidsynchronization
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent introduces a change detection mechanism as an intermediary between the display controller and display driver integrated circuit. This intermediary monitors content changes and triggers synchronization signal provision only when necessary. The intermediary layer allows the controller to remain powered off during static content display while ensuring synchronization is maintained when content changes occur.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system performs preliminary detection of content changes before determining whether to activate the display controller. By checking in advance whether the displayed content has changed, the system can proactively decide to keep the controller powered off during static periods, and only activate when a change is detected, thus maintaining synchronization reliability without continuous power consumption.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP4621762A1Low power display timing synchronization between soc and display driver integrated circuit
Publication Date: 2025.09.24 MEDIATEK INC
  • EP4621762A1 patent drawingFigure 1
  • EP4621762A1 patent drawingFigure 2
  • EP4621762A1 patent drawingFigure 3

AI summary

An electronic device (200) includes a display controller (110), a clock generator (210), a multiplexer (220), and a processor (120). The display controller (110) includes an interface (111), where the display controller (110) provides a synchronization signal through the interface (Ill). The clock generator (210) generates a clock signal. The multiplexer (220) outputs either the synchronization signal or the clock signal as an output signal. When the processor (120) needs to reduce power consumption of the display controller (110), the processor controls (120) the multiplexer (220) to output the clock signal as the output signal.