SoC Distributed DMA Controller for DRAM Access Bottlenecks
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Solution Overview
Problem
System-on-a-Chip (SoC) with multiple processors experiences low data transmission efficiency and lengthy delays due to insufficient bandwidth of the memory controller when accessing dynamic random access memory (DRAM).
Innovation Solution
The implementation of a data access system that includes a System-on-a-Chip (SoC) with a handling module comprising a DMA controller, an arbiter, and a memory controller, which allocates memory address space for each processor and uses direct memory access (DMA) and arbitration to manage bus requests, improving access speed by allowing processors to directly access DRAM through a PCIe bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple processors share a large memory pool through bus mode, then memory capacity is increased, but data transmission efficiency decreases and delay increases
Solution Approach 1:
The patent divides the shared memory pool into private memory spaces for each processor by allocating memory address spaces individually. Each processor has its own dedicated memory region that can be accessed directly without going through the shared bus, thereby segmenting the memory access path and eliminating bus contention while maintaining the large total memory capacity through the memory pool.
Solution Approach 2:
The patent introduces a memory controller as an intermediary component that manages direct memory access requests from processors to the DRAM. The memory controller acts as a mediator that allocates memory address spaces to processors and facilitates direct access without requiring processors to share the bus, thus improving data transmission efficiency while maintaining memory capacity.
2Device complexity
If a single memory controller accesses DRAM through bus mode, then device complexity is reduced, but bandwidth is insufficient and access speed is slow
Solution Approach 1:
The patent segments the memory access function by assigning dedicated memory address spaces to each processor. Each processor can directly access its allocated memory region through direct memory access (DMA) without requiring the single memory controller to mediate all access through the bus. This segmentation enables parallel memory access paths, significantly improving access speed while keeping the overall device complexity manageable through structured address space allocation.
3Device complexity
If multiple processors transmit data through shared bus, then device complexity is reduced, but data transmission efficiency is low and delay is lengthy
Solution Approach 1:
The patent extracts the memory access function from the shared bus architecture by implementing direct memory access (DMA) for each processor. Each processor can directly access its allocated memory address space without going through the bus, effectively taking out the memory access path from the bus-based communication mechanism. This eliminates bus contention and reduces data transmission delay significantly.
Solution Approach 2:
The patent introduces DMA controllers as intermediary components that enable direct memory access for each processor. These DMA controllers act as mediators that manage direct access to memory address spaces without requiring processors to share the bus. This intermediary mechanism eliminates the need for bus-based data transmission, significantly reducing transmission delay while maintaining manageable device complexity through structured DMA control.
Data Source
AI summary
A method of providing more efficient and streamlined data access to DRAM storage medium by all of multiple processors within a system on a chip (SoC) requires every processor to send use-of-bus request. When the request is for local access (that is, for access to that part of DRAM which is reserved for that processor), the processor reads or writes to the DRAM storage medium through its own arbitrator and own memory controller. When the request is for non-local access (that is, to DRAM within the storage medium which is reserved for another processor), the processor reads or writes to the “foreign” address in the storage medium through its own arbiter, its own memory controller, and its own DMA controller. A data access system is also disclosed.