SoC Distributer-Aggregator Architecture for Packet Processing Throughput
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Solution Overview
Problem
Current SoC designs face challenges in optimizing packet processing performance due to the limitations of using a single processing element, which restricts throughput and requires complex design changes to accommodate varying packet types and scheduling policies.
Innovation Solution
The implementation of a system-on-chip (SoC) with multiple processing elements and a distributer-aggregator architecture that determines a scheduling policy based on packet type, distributing request packets accordingly and aggregating response packets, allowing for improved processing performance without altering surrounding components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single processing element is used, then device complexity is reduced, but processing throughput and performance are limited
Solution Approach 1:
The processing system is divided into multiple independent processing elements (PE0, PE1, PE2, etc.), each capable of handling specific packet types. The distributer segments the incoming packet stream and routes different packet types to appropriate processing elements, enabling parallel processing and improved throughput without requiring complex inter-element communication protocols.
2Productivity
If multiple processing elements are used, then processing throughput is improved, but design complexity of surrounding components increases
Solution Approach 1:
The distributer acts as an intermediary between the packet source and multiple processing elements, implementing scheduling policies based on packet types. The aggregator serves as another intermediary that collects results from processing elements and reconstructs the original packet sequence. These intermediary components simplify the overall system design by centralizing the complexity of multi-element coordination.
3Productivity
If packet processing is optimized for specific packet types, then processing performance is improved, but adaptability to varying packet types decreases
Solution Approach 1:
Each processing element is designed to handle specific packet types efficiently, while the distributer provides universal routing capabilities that can adapt to any packet type by selecting appropriate processing elements. The aggregator universally collects and reconstructs packets regardless of their types, making the overall system both specialized for performance and universal in adaptability.
4Productivity
If design changes are made to accommodate multiple processing elements, then processing performance is improved, but ease of manufacture and integration decreases
Solution Approach 1:
The distributer and aggregator serve as standardized intermediary interfaces that simplify integration. Existing packet processing components can be manufactured independently and then integrated through these standard interfaces, reducing the complexity of manufacturing and system integration while still enabling multi-element parallel processing for improved performance.
Data Source
AI summary
A system-on-chip includes a first intellectual property (IP) generating a plurality of request packets; and a second IP generating a plurality of response packets based on the plurality of request packets, wherein the second IP includes a plurality of processing elements processing the plurality of request packets and generating the plurality of response packets; a distributer, when the plurality of request packets are input from the first IP, determining a scheduling policy based on a packet type of the plurality of request packets and distributing the plurality of request packets to the plurality of processing elements according to the determined scheduling policy; and an aggregator, when the plurality of response packets are received from each of the plurality of processing elements, aggregating the plurality of response packets according to the determined scheduling policy.