SoC Signal Integrity Testing via DQS Delay and Margin Analysis
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed signal transfer between System on Chip (SoC) and memory devices in mobile devices leads to signal integrity issues such as ringing, crosstalk, and ground bounce, causing malfunction, necessitating a method to test and ensure signal integrity.
Innovation Solution
A method involving delaying the data strobe signal, obtaining setup and hold margins, and determining a data valid window to assess signal integrity by comparing it with a threshold value, using a memory controller with a DQS delay circuit and latches to control the physical interface and generate selection signals for margin calculation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the signal speed is increased to achieve high performance, then the data transfer rate is improved, but signal integrity problems such as ringing, crosstalk, and ground bounce occur
Solution Approach 1:
The patent applies preliminary action by performing signal integrity testing before actual data transmission occurs. The test program proactively identifies potential signal integrity issues by measuring setup and hold margins under various operating conditions, allowing the system to prevent problematic high-speed operations before they cause ringing, crosstalk, or ground bounce effects.
Solution Approach 2:
The patent implements feedback through the test program that continuously monitors and measures signal characteristics. By comparing the measured setup and hold margins against predetermined thresholds, the system receives feedback about signal integrity status and can adjust operating parameters or alert the user to potential issues, thereby maintaining reliable operation at high speeds.
2Productivity
If the signal speed is increased to achieve high performance, then the data transfer rate is improved, but signal integrity problems cause malfunction
Solution Approach 1:
The test program performs preliminary assessment of signal integrity by measuring setup and hold margins before high-speed data transfer begins. This proactive testing identifies potential causes of malfunction such as excessive ringing or crosstalk, allowing the system to either adjust operating parameters or warn the user before productivity-critical operations fail.
Solution Approach 2:
The system continuously feedbacks on signal integrity status during operation. The test program monitors signal characteristics in real-time and compares them against safety thresholds, providing feedback that triggers corrective actions or alerts when signal quality deteriorates to levels that could cause malfunction during high-speed data transfer.
3Reliability
If a test program is executed to assess signal integrity, then the reliability is improved, but the operation time is increased
Solution Approach 1:
The patent applies partial action by implementing a streamlined test program that measures only the critical setup and hold margins rather than performing exhaustive signal integrity analysis. The test focuses on the most important parameters (setup and hold times) that directly impact signal integrity, thereby achieving reliable assessment with minimal time investment rather than excessive comprehensive testing.
Data Source
AI summary
A method of operating a system on chip (SoC), an integrated circuit including the SoC, and a system including the same are provided. The method includes: delaying a data strobe signal; obtaining a setup margin and a hold margin by adjusting a delay of the delayed data strobe signal; and determining a data valid window using the obtained setup margin and the obtained hold margin.