3D Stacked SOC and DRAM Package Assembly with TSV Interconnects
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Solution Overview
Problem
Current semiconductor package assemblies face challenges in achieving optimal signal pad to ground pad ratio for improved coupling effects, bandwidth, latency, power efficiency, weight reduction, and form factor, particularly in memory applications with increased integration levels.
Innovation Solution
A semiconductor package assembly is designed with a hybrid configuration, featuring a system-on-chip (SOC) package and dynamic random access memory (DRAM) packages stacked vertically, utilizing through-silicon vias (TSV) interconnects and redistribution layers (RDL) to connect the SOC and DRAM dies, along with a molding compound for encapsulation, allowing for varied pin configurations and efficient signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory applications use increased levels of integration to improve performance and bandwidth, then component density and functionality are improved, but the signal pad to ground pad ratio becomes suboptimal and coupling effects deteriorate
Solution Approach 1:
The patent transitions from planar 2D packaging to 3D vertical stacking architecture. Multiple memory packages are stacked vertically with intermediate transfer boards, creating three-dimensional signal routing paths. This dimensional change allows optimization of pad ratios in each layer while maintaining overall high integration, resolving the contradiction between integration level and coupling effect.
Solution Approach 2:
The memory system is divided into multiple discrete packages stacked vertically, with signal transmission segmented across different layers and intermediate transfer boards. This segmentation allows each package to maintain optimal pad ratios independently while achieving high overall integration through vertical interconnection.
2Volume of moving object
If more semiconductor packages are stacked vertically to increase component density, then form factor and weight are reduced, but manufacturing complexity and assembly difficulty increase
Solution Approach 1:
The intermediate transfer board serves multiple functions: it acts as a mechanical support structure, provides electrical interconnection between stacked packages, enables signal routing, and facilitates thermal management. This multi-functionality reduces the need for additional specialized components, thereby managing manufacturing complexity despite increased vertical stacking.
Solution Approach 2:
Intermediate transfer boards are introduced as mediator components between stacked memory packages. These intermediaries simplify the interconnection architecture by providing standardized interfaces and signal routing layers, making the assembly process more manageable compared to direct package-to-package interconnection.
3Power
If the number of I/O pins is increased to improve signal transmission capacity, then bandwidth is improved, but power consumption and device complexity increase
Solution Approach 1:
Different packages and layers are assigned different I/O pin configurations based on their specific functional requirements. The intermediate transfer boards provide localized signal routing that optimizes the signal pad to ground pad ratio in each region, allowing high bandwidth where needed while minimizing power consumption in other areas, rather than uniformly increasing I/O pins across the entire system.
Data Source
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AI summary
The invention provides a semiconductor package assembly including a system-on-chip (SOC) package. The SOC package includes a logic die having first pads thereon. A first redistribution layer (RDL) structure is coupled to the logic die. A molding compound surrounds the logic die, being in contact with the first RDL structure and the logic die. A dynamic random access memory (DRAM) package is stacked on the SOC package. The DRAM package includes a body having a die-attach surface and a bump-attach surface opposite to the die-attach surface. A dynamic random access memory (DRAM) die is mounted on the die-attach surface, coupled to the body through the bonding wires. One of the SOC package and the DRAM package includes an additional dynamic random access memory (DRAM) die embedded therein. The additional DRAM die has through silicon via (TSV) interconnects formed through the additional DRAM die.