SoC Voltage Droop Compensation via Clock Stretching
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Solution Overview
Problem
Integrated circuits face voltage droops due to rapid changes in power demand, leading to slower operation and combinatorial logic failures, particularly in System-on-Chip (SoC) devices, where voltage droops are not uniform, causing timing failures and increased delay in logic paths.
Innovation Solution
Implementing a system with droop monitors and clock adjustment circuitry to detect voltage droops and temporarily stretch the clock period, reducing load current and droop amplitude, using distributed droop monitors and a clock stretcher scheme to prevent logic failures, including analog and digital implementations of delay lines for monitoring and clock phase adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If voltage regulation circuits are used to supply power to integrated circuits, then power delivery is provided, but voltage droops occur during rapid increases in power demand
Solution Approach 1:
The droop monitor detects voltage droops before they cause logic failures, and the clock adjustment circuitry proactively stretches the clock period in anticipation of timing failures. This preliminary action prevents the harmful effect of voltage droop by preparing the system in advance, allowing logic paths to complete their operations despite reduced voltage levels.
Solution Approach 2:
The system applies counter-action by stretching the clock period when a droop is detected, which reduces the switching activity and consequently reduces the load current that causes the voltage droop. This preliminary anti-action offsets the harmful effect of the droop by reducing the demand that created it.
2Productivity
If clock frequency is maintained at high levels, then system performance is improved, but timing failures occur during voltage droops
Solution Approach 1:
The clock adjustment circuitry dynamically modifies the clock period based on real-time voltage conditions. When a droop is detected, the clock period is stretched (frequency reduced) to allow logic paths more time to complete their operations. This dynamic adjustment maintains timing accuracy during droops while preserving high performance during normal operation.
Solution Approach 2:
The system changes the clock period parameter in response to detected voltage droops. By extending the clock period, the system provides additional time for signal propagation through logic paths, compensating for the increased delay caused by reduced voltage levels and preventing timing failures.
3Reliability
If clock period is stretched to prevent logic failures, then timing reliability is improved, but system performance is throttled
Solution Approach 1:
The clock period is stretched only partially and only when necessary, based on the detection of actual voltage droops. The system applies the minimum necessary adjustment to prevent timing failures, rather than continuously throttling performance. This partial action maintains timing reliability during droop events while minimizing the impact on overall system performance.
Solution Approach 2:
The clock adjustment is applied periodically and temporarily, only during the duration of detected voltage droop events. The system monitors voltage continuously and applies clock stretching only when droops occur, allowing full performance during normal operation and providing targeted protection during transient conditions.
4Measurement precision
If distributed droop monitors are implemented across SoC die, then detection precision is improved, but device complexity increases
Solution Approach 1:
The SoC is divided into multiple regions, each with its own droop monitor, allowing localized detection of voltage droops in different parts of the chip. This segmentation enables precise identification of where droops occur, which is particularly important in large SoCs where voltage drops may be non-uniform across the die.
Solution Approach 2:
The droop monitor circuitry uses a universal detection mechanism that can be replicated across multiple locations. Each monitor performs the same function of detecting voltage droops in its local region, providing a scalable approach that improves detection precision without requiring fundamentally different circuit designs for each location.
Data Source
AI summary
Droop monitors spread across a system-on-chip (SoC) monitor for voltage droops in regulated supply voltage supplied to logic circuitry of the SoC. In the event of a voltage droop, a clock signal supplied to the logic circuitry is stretched, to temporarily increase a period of the clock signal. The droop monitors may include a sensing delay line provided voltage at the regulated supply voltage, and a reference delay line supplied with a reference voltage, with operations of the delay lines monitored to determine a voltage droop.