SoC Dual Boot Loader Architecture for Rapid Wake-Up

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Solution Overview

Problem

Existing systems face challenges in quickly waking up a computer system from a power-down mode while maintaining efficient power management and reducing boot time.

Innovation Solution

A System on Chip (SoC) is designed to use two independent boot loaders for booting and wake-up sequences, allowing for selective use of boot loaders stored in different locations to quickly initiate the operating system code, even from a power-down mode.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If a single boot loader is used for both booting and wake-up sequences, then device complexity is reduced, but wake-up time increases and power consumption increases

Engineering Contradiction:

Improvewake-up timeVSAvoidboot loader structure

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent divides the boot loader functionality into two separate boot loaders: a first boot loader for initial booting operations and a second boot loader for wake-up operations. This segmentation allows each boot loader to be optimized for its specific function, enabling faster wake-up times without requiring the entire boot sequence to restart from scratch.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The second boot loader is pre-loaded into SRAM memory during the initial booting process, so that when the system needs to wake up from power-down mode, the boot loader is already available in fast memory. This preliminary action eliminates the need to re-load the boot loader from slower storage during wake-up operations.

Inventive Principle:

Principle #10Preliminary action

2Use of energy by stationary object

If the entire system is powered down completely, then power consumption is reduced, but wake-up time increases due to full re-initialization

Engineering Contradiction:

Improvepower consumptionVSAvoidwake-up time

Core Design Contradiction:

Use of energy by stationary objectVSLoss of time

Solution Approach 1:

The second boot loader is loaded into SRAM during the initial booting sequence and remains there even when the system enters power-down mode. This preliminary placement of the boot loader in fast memory ensures that upon wake-up, the system can immediately execute the boot loader without re-loading it from slower storage, thus reducing wake-up time while maintaining low power consumption during the powered-down state.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent applies different power management strategies to different memory components: SRAM maintains power supply to preserve the second boot loader, while other system components can be fully powered down. This local quality approach allows selective power management that balances between power consumption and wake-up speed.

Inventive Principle:

Principle #3Local quality

3Quantity of substance

If flash-based memory is used for boot loader storage, then storage capacity is increased, but memory lifespan decreases due to frequent write operations during wake-up

Engineering Contradiction:

Improvestorage capacityVSAvoidmemory lifespan

Core Design Contradiction:

Quantity of substanceVSDuration of action of stationary object

Solution Approach 1:

The patent extracts the second boot loader from flash-based memory and loads it into SRAM during the initial booting process. By taking out the boot loader from flash storage and placing it in volatile memory, the system eliminates the need for frequent read/write operations to flash during wake-up sequences, thereby extending the lifespan of the flash-based storage while maintaining adequate storage capacity.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The second boot loader is pre-loaded into SRAM during the initial booting sequence, so that subsequent wake-up operations do not require accessing flash memory. This preliminary action consolidates all flash access to occur only once during initial booting, significantly reducing wear on the flash-based storage and extending its operational lifespan.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20250165054A1System on chip for reducing wake-up time, method of operating same, and computer system including same

Publication Date: 2025.05.22 SAMSUNG ELECTRONICS CO LTD

AI summary

A system on chip (SoC) includes an internal read-only memory (ROM) configured to store a first boot loader; a first internal static random access memory (SRAM) configured to receive a second boot loader output from a booting device, store the second boot loader, and perform a booting sequence according to control of the first boot loader; a second internal SRAM configured to receive a third boot loader output from the booting device, store the third boot loader, and perform a wake-up sequence according to control of the first boot loader; and a dynamic random access memory (DRAM) controller configured to load an operating system (OS) from the booting device into a DRAM according to control of the second boot loader.