SoC DVFS Control via Execution Queue Residence Time
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Solution Overview
Problem
Conventional DVFS techniques in mobile devices react slowly to changes in CPU load, often adjusting frequency based on past task loads rather than current loads, leading to inadequate frequency determination and poor management of sudden increases in task load.
Innovation Solution
A method and system for a System on Chip (SoC) that calculates residence times for tasks in execution queues, adjusting CPU frequency and voltage based on these times to quickly respond to current task loads, including measuring entry and exit times, calculating unit residence times, and generating interrupts for frequency adjustments when reference times are exceeded.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional DVFS techniques adjust CPU frequency based on recent CPU load observation, then the system can maintain stable operation, but the reaction speed is slow when CPU performance is needed immediately
Solution Approach 1:
The patent pre-calculates and stores task load information in an execution queue before tasks are actually executed. This allows the DVFS controller to access accurate load information immediately when needed, rather than waiting for observation-based estimation to catch up. The execution queue maintains task metadata including load characteristics, enabling proactive frequency adjustment decisions.
Solution Approach 2:
The patent introduces an execution queue as an intermediary data structure between task submission and CPU execution. This queue stores task information including load characteristics, allowing the DVFS controller to query accurate load data without directly observing running tasks. The execution queue acts as a buffer that decouples the measurement timing from the control decision timing.
2Speed
If conventional DVFS techniques adjust frequency based on current task load, then the frequency can be determined for current tasks, but it cannot predict or prepare for future task loads
Solution Approach 1:
The execution queue stores task load information in advance before tasks are executed. When a task is submitted to the queue, its load characteristics are captured and stored. This preliminary storage of load information allows the DVFS controller to prepare frequency adjustments ahead of time, reducing the lag when tasks actually execute.
Solution Approach 2:
The patent implements dynamic frequency adjustment by continuously monitoring the execution queue for upcoming tasks with high load characteristics. The DVFS controller dynamically changes frequency based on the composition of tasks in the queue, allowing the system to proactively adapt to anticipated load changes rather than reacting passively to current load.
3Productivity
If conventional DVFS techniques use simple load observation, then the system complexity is low, but the system cannot quickly manage abrupt increases in task load
Solution Approach 1:
The execution queue serves as an intermediary that captures task load information at submission time. This queue structure provides the DVFS controller with ready-accessible load data without requiring complex real-time observation mechanisms. The queue naturally organizes task information, making it easy to query upcoming load without adding significant system complexity.
Solution Approach 2:
The patent implements a feedback mechanism where the DVFS controller continuously monitors the execution queue for changes in task composition and load characteristics. When the queue contains tasks with high load or when load patterns change, the controller provides feedback by adjusting the CPU frequency. This closed-loop feedback enables quick response to load changes using relatively simple queue-based monitoring.
Data Source
AI summary
A method of operating a system on chip (SoC) includes calculating a first residence time indicating an amount of time that at least one task resides in an execution queue in the SoC, wherein the at least one task is assigned to at least one core of a multi-core processor in the SoC, calculating a total unit residence time indicating an amount of time that all tasks other than the at least one task reside in the execution queue, calculating a second residence time for the at least one core by adding the first residence time of the at least one task and the total unit residence time, and adjusting at least one of an operating frequency and a voltage of the at least one core based on the second residence time.