SoC Dynamic Voltage Scaling via Load Current Estimation
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Solution Overview
Problem
Conventional System on Chip (SoC) devices face high power consumption due to fixed target voltage, leading to unnecessary power consumption and rapid changes in power voltage caused by clock signal transitions, which result in overshoot and undershoot voltages.
Innovation Solution
A system on chip device with a micro controller unit and internal clock generation unit that estimates changes in operating current to dynamically adjust the target voltage, reducing overshoot and undershoot voltages by generating clock enable signals and internal clock signals for application circuits, thereby controlling power voltage dynamically.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the power voltage is increased to maintain operation during load current transitions, then the reliability is improved, but the power consumption increases and overshoot/undershoot voltages occur
Solution Approach 1:
The patent implements dynamic power voltage adjustment by transitioning from a fixed target voltage to a dynamically adjustable target voltage that adapts to load current changes. The power management unit modifies the target voltage in response to detected load current transitions, allowing the system to maintain reliable operation during transient conditions while reducing unnecessary power consumption during steady-state operation.
Solution Approach 2:
The patent changes the parameter of target voltage from a fixed value to a variable parameter that can be adjusted based on operating conditions. By modifying the target voltage parameter in response to load current changes, the system optimizes the balance between maintaining operational reliability and minimizing power consumption, preventing both excessive power usage and voltage instability.
2Reliability
If a fixed target voltage is used to ensure stable operation, then the reliability is improved, but the device complexity increases due to voltage margin requirements
Solution Approach 1:
The patent implements a feedback mechanism where the power management unit continuously monitors load current changes and adjusts the target voltage accordingly. This closed-loop control eliminates the need for excessive voltage margins by actively compensating for load transitions, thereby maintaining operational stability while simplifying the voltage control system compared to fixed high-margin designs.
Solution Approach 2:
The patent applies preliminary action by detecting load current transitions and adjusting the target voltage before significant overshoot or undershoot occurs. This proactive voltage adjustment prevents operational instability without requiring excessive voltage margins, thereby reducing device complexity while maintaining reliability.
3Use of energy by moving object
If the target voltage is adjusted dynamically to reduce power consumption, then the power consumption decreases, but the device complexity increases
Solution Approach 1:
The patent implements self-service by enabling the power management unit to automatically detect load current changes and adjust the target voltage without external intervention. This autonomous operation reduces power consumption through dynamic voltage scaling while avoiding the complexity of external control mechanisms, as the system manages its own power optimization.
Solution Approach 2:
The patent uses feedback control where the power management unit monitors system conditions and automatically adjusts the target voltage to optimize power consumption. This closed-loop approach achieves dynamic voltage scaling with minimal added complexity, as the feedback mechanism integrates seamlessly with existing power management infrastructure.
4Productivity
If the clock signals are enabled for all application circuits, then the productivity is improved, but the power consumption increases due to unnecessary clock distribution
Solution Approach 1:
The patent applies local quality by enabling clock signals selectively for specific application circuits based on their operational needs rather than uniformly for all circuits. The microcontroller unit generates clock enable signals that are locally applied to individual circuits, allowing high productivity in active circuits while minimizing power consumption in inactive circuits by disabling their clock distribution.
Data Source
AI summary
A system for dynamically scaling a power voltage including a system on chip (SoC) and a power control circuit. The SoC includes a plurality of application circuits. The SoC is configured to generate internal clock signals in response to an externally supplied clock signal. The SoC also generates a target voltage that changes based on a change of an operating current. The internal clock signals are respectively provided to the application circuits. The operating current is a sum or total current of the application circuits. The power control circuit generates an internal power voltage based on the target voltage and provides the internal power voltage to the SoC. The system for dynamically scaling a power voltage including a SoC may decrease power consumed in the SoC because the system of dynamically scaling a power voltage decreases a required voltage margin by changing a target voltage before a transition of the SoC current.