Error Detection Unit for SoC Data Integrity
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Solution Overview
Problem
In System-on-Chip (SoC) devices, undetected data errors can propagate and lead to cascading failures due to the integration of multiple core devices on a single chip, where data corruption can occur from various sources like malicious entities, hardware malfunctions, or software corruption, posing a risk to the integrity of data communication.
Innovation Solution
A method for error detection within an integrated circuit chip that analyzes transactions over interconnect circuitry and scans memory for data errors, using techniques like cyclic redundancy checks and hash value comparisons, with dedicated actions such as error correction, alert generation, or blocking access to corrupted data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple core devices are integrated onto a single chip to reduce product size, then product size is reduced, but data error propagation risk increases
Solution Approach 1:
The patent introduces an error detection unit as an intermediary component between the interconnect circuitry and core devices. This unit monitors transactions on the interconnect bus, detects data errors using techniques like cyclic redundancy checks, and prevents corrupted data from propagating to multiple core devices, thus resolving the reliability issue while maintaining the integrated chip architecture.
2Reliability
If error detection and memory scanning are performed continuously to ensure data integrity, then data integrity is improved, but processing overhead and performance impact increase
Solution Approach 1:
The patent implements periodic error detection and memory scanning rather than continuous monitoring. The error detection unit scans memory at predetermined time intervals or when specific conditions are met (e.g., when the interconnect circuitry is free), balancing data integrity assurance with minimal impact on processing throughput.
3Reliability
If error detection and correction mechanisms are implemented to prevent data corruption, then data integrity is improved, but device complexity increases
Solution Approach 1:
The patent extracts the error detection and correction functionality into a separate, dedicated error detection unit that operates independently from the core devices. This modular approach allows comprehensive error detection capabilities to be implemented without significantly increasing the complexity of each individual core device, as the detection logic is centralized in a specialized component.
Data Source
AI summary
A method of performing error detection within an integrated circuit chip analyses transactions communicated over interconnect circuitry of the integrated circuit chip to detect whether a message contains a data error. A memory of the integrated circuit chip coupled to the interconnect circuitry is scanned to detect whether there is a data error stored in the memory, and in response to detecting a data error in a transaction communicated over the interconnect circuitry and/or a data error stored in the memory, a dedicated action indicative of a data error is performed.