SoC Error Handling via Single Interrupt and Buffer
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Solution Overview
Problem
Current systems-on-chip (SoC) face complexity in detecting and reporting fatal errors due to the need for hundreds of interrupt bits and thousands of error context registers, making error handling cumbersome and inefficient.
Innovation Solution
A system and method that utilize a single interrupt and buffer to report and handle multiple errors from a SoC platform, processing each error sequentially and prioritizing them, thereby reducing the number of interrupt bits and special function registers required, and maintaining a design state until errors are processed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If one interrupt bit and error context are dedicated for each error in SOC, then error detection capability is improved, but device complexity and firmware complexity increase significantly
Solution Approach 1:
Multiple individual error interrupt bits and their corresponding status registers are merged into a single consolidated error interrupt mechanism. The error handler aggregates error information from multiple sources and reports them through one unified interrupt, reducing the number of interrupt bits and status registers while maintaining the ability to detect and report multiple error conditions.
Solution Approach 2:
The single error interrupt and associated status register are designed to handle multiple different error types universally. Instead of having dedicated interrupt bits for each error type, the universal error interrupt can be triggered by any error condition, and the status register contains information about the specific error type, making the system multi-functional with fewer components.
2Reliability
If one interrupt bit and error context are dedicated for each error in SOC, then error detection capability is improved, but firmware complexity increases
Solution Approach 1:
The firmware error handling is simplified by merging multiple error handling routines into a single unified error handler. Instead of managing hundreds of individual interrupt service routines, the firmware implements one error handler that processes errors from multiple sources through a standardized interface, significantly reducing firmware complexity.
Solution Approach 2:
An error handler acts as an intermediary layer between the hardware error sources and the firmware. This intermediary aggregates error information from multiple hardware sources and presents a simplified interface to the firmware, reducing the burden on firmware developers while maintaining comprehensive error detection capabilities.
3Reliability
If hundreds of interrupt bits and thousands of error context registers are used, then comprehensive error coverage is achieved, but logic complexity increases
Solution Approach 1:
Multiple error context registers are merged into a single consolidated status register that contains information about multiple error conditions. Instead of having separate registers for each error type, the unified status register encodes multiple error states, reducing the number of registers while maintaining comprehensive error information.
Solution Approach 2:
The error information representation transitions from a distributed structure (many interrupt bits and registers) to a consolidated structure (single interrupt and register with encoded information). This dimensional change packs multiple error states into fewer resources by using bit fields and encoding schemes within the unified register.
Data Source
AI summary
A system for error reporting and handling includes a memory storing an error handler, a processor configured to execute the error handler, and a buffer. The error handler is configured to receive an error message from a system on chip (SOC) platform. The error message indicates a plurality of errors have occurred in the SOC platform, and the buffer stores the error message. Further, the error handler is configured to report the error message using a single interrupt. Further, the error handler is configured to handle the errors in the error message using the single interrupt.