SoC Fast Path Enabler for Packet Latency
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Solution Overview
Problem
In data plane applications on system-on-a-chip (SoC) architectures, packet processing experiences unpredictable latencies due to varying performance across different clusters and processing elements, leading to reduced performance and indeterminism.
Innovation Solution
The implementation of SoC-Aware Fast Path Enablers (SAFPE) that learn the SoC architecture during boot time and pre-fetch data packets to a common cache, reducing DDR latency and minimizing data movement between clusters by executing instructions to optimize data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If packet processing traverses through multiple PEs in different clusters on SoC, then processing capability is improved, but latency becomes unpredictable and performance decreases
Solution Approach 1:
The SAFPE component performs preliminary actions by learning the SoC architecture topology during boot time and pre-fetching data packets to a common cache before actual packet processing occurs. This advance preparation ensures that when packets need to be processed across multiple PEs, the data is already positioned in optimal locations, eliminating unpredictable latency during actual processing.
Solution Approach 2:
The patent introduces a SAFPE (SoC-Aware Fast Path Enabler) component as an intermediary between the packet dispatcher and the processing elements. This intermediary learns the SoC architecture, determines optimal PE assignments, and manages data movement between caches and PEs, thereby mediating the complex interactions that cause unpredictable latency while maintaining high processing capability.
2Reliability
If special CPU instructions are executed to avoid unpredictable latencies, then latency predictability is improved, but the solution does not consider SoC architecture and focuses on particular PEs
Solution Approach 1:
The SAFPE component dynamically adapts to the specific SoC architecture by learning its topology during boot time and adjusting its packet routing and data pre-fetching strategies based on the actual cluster and PE configuration. This dynamic adaptation allows the system to maintain latency predictability while being versatile across different SoC architectures, rather than being fixed to particular PEs or static CPU instructions.
Data Source
AI summary
In a typical data plane application, there is a packet dispatcher which receives packets from the underlying subsystem for distribution among various threads/processes for further processing. These threads/processes may run on various processing elements (PEs) and pass through multiple stages of processing. As new generation system-on-a-chip (SoC) architectures have multiple heterogeneous clusters with corresponding PEs, packet processing may traverse through multiple PEs in different clusters. Since latencies/performance for different clusters/PEs may be different, packet processing on the SoC may take a variable amount of time, which may lead to unpredictable latencies. The present disclosure provides embodiments to solve the problem of packet processing on heterogeneous clusters/PEs by providing a fast path enabler to the applications for SoC architecture awareness. The fast path enabler understands the cache topology of the SoC and may pre-fetch packets to the desired cache to minimize latencies for improved performance.