SOC FPGA Control for Medium Voltage VFD
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Solution Overview
Problem
Current medium voltage variable frequency drive systems require a considerable amount of physical space and are prone to system failures due to the use of multiple separate components for control loop command, status, and external communications, which increases the probability of manufacturing defects and usage-related issues.
Innovation Solution
A control system integrating a system on chip (SOC) with one or more central processing units and a field programmable gate array (FPGA) to consolidate control functions, reducing the need for a dedicated data bus and minimizing physical space, while enhancing robustness by reducing the number of components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If three separate components (control processor, FPGA, EPLD) are used for control functions, then control functionality is comprehensive, but physical space requirement increases and system reliability decreases
Solution Approach 1:
The patent merges the control processor, FPGA, and EPLD into a single integrated control system component. This consolidation reduces the number of separate devices from three to one, thereby decreasing the probability of system failure due to manufacturing defects or usage issues while maintaining all necessary control functionalities including control loop commands, power cell control, and external communications.
2Ease of manufacture
If three separate components are used with dedicated data bus, then control functions are separated and manageable, but PCB space and trace engineering complexity increase
Solution Approach 1:
The patent consolidates multiple control functions into a single integrated component that requires fewer dedicated data bus connections. This merging reduces the PCB trace layout complexity and the physical area required on the PCB, as the integrated component has fewer interconnection requirements compared to three separate components each needing dedicated data bus traces.
3Reliability
If multiple separate components are used, then functional separation is achieved, but probability of system failure increases
Solution Approach 1:
The patent integrates control processor, FPGA, and EPLD functions into one unified control system component. This consolidation directly reduces the probability of overall system failure by minimizing the number of potential failure points from three separate components to a single integrated unit, while preserving all necessary control functionalities through internal integration.
Data Source
AI summary
A drive system (300) includes a plurality of power cells (312) supplying power to one or more output phases (A, B, C), each power cell (312) having multiple switching devices (315a-d) incorporating semiconductor switches, and a control system (400) in communication with the plurality of power cells (312) and controlling operation of the plurality of power cells (312), wherein the control system (400) includes a system on chip (410) with one or more central processing units (412, 414) and a field programmable gate array (416) in communication with the one or more central processing units (412, 414).