Multi-core SoC Frequency Tagging for Dynamic Task Allocation

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Solution Overview

Problem

Multi-core processors face inefficiencies due to differences in operating frequencies among cores, leading to suboptimal performance and power consumption, as existing systems often rely on the slowest core's frequency for task distribution, limiting the potential of faster cores.

Innovation Solution

Incorporating a critical path monitoring circuit in each core to measure and tag its maximum operating frequency, allowing the operating system to dynamically allocate tasks to the fastest available core, thereby improving performance without significantly increasing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the system uses the slowest core's frequency for task distribution, then all cores can operate at a uniform frequency, but the faster cores cannot operate at their optimal frequency, reducing overall system performance

Engineering Contradiction:
Improvesystem performanceVSAvoidfrequency adaptation
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent applies local quality by allowing each core to operate at its own optimal frequency rather than forcing uniform frequency across all cores. The system measures and tags each core's maximum operating frequency, then distributes tasks to cores based on their individual frequency capabilities, enabling faster cores to run at higher frequencies while slower cores operate at their appropriate speeds.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements dynamics by making the frequency assignment adaptive rather than static. The system dynamically measures each core's maximum operating frequency using critical path monitoring circuits, stores these measurements in device control registers, and continuously adapts task distribution decisions based on the measured frequency characteristics of each core.

Inventive Principle:
Principle #15Dynamics

2Productivity

If tasks are distributed without considering individual core frequencies, then task distribution is simple, but the system fails to utilize the full potential of faster cores

Engineering Contradiction:
Improvecore utilization efficiencyVSAvoidtask distribution complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by measuring and storing each core's maximum operating frequency in advance before task distribution occurs. The critical path monitoring circuits measure the frequency characteristics during manufacturing or initialization, and these measurements are stored in device control registers, so that when tasks need to be distributed, the system can immediately query the pre-stored frequency information without performing complex real-time measurements.

Inventive Principle:
Principle #10Preliminary action

3Stability of the object's composition

If the system attempts to equalize all core frequencies, then uniform operation is achieved, but the faster cores are forced to operate below their optimal frequency

Engineering Contradiction:
Improveoperational uniformityVSAvoidprocessing speed
Core Design Contradiction:
Stability of the object's compositionVSProductivity

Solution Approach 1:

The patent applies parameter changes by varying the operating frequency parameter for each core based on its individual characteristics. Instead of maintaining a single uniform frequency parameter for all cores, the system measures and stores individual frequency parameters for each core in device control registers, then selects appropriate frequency parameters for task execution based on the measured characteristics, allowing each core to operate at its optimal frequency point.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8566836B2Multi-core system on chip
Publication Date: 2013.10.22 VLSI TECHNOLOGY LLC
  • US8566836B2 patent drawing
  • US8566836B2 patent drawing
  • US8566836B2 patent drawing

AI summary

A multi-core system on a chip (200) is described in which a speed information for each core (210, 220, 230, 240), such as the maximum operation speed (Fmax), is extracted and stored in a storage device, such as a device control registry (215), where it may be accessed and used by the operating system when allocating workload among the cores by selecting the fasted core (e.g, 210) to run any applications or tasks that can not be executed on a plurality of cores.