SoC Reset Testing Through Functional Paths and Clock Synchronization
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Solution Overview
Problem
Conventional reset test systems for system-on-chip (SoC) devices do not adequately test the functional reset paths, leading to reduced test coverage and incomplete verification of components and IP blocks during the reset test process.
Innovation Solution
A reset test system that allows a test reset to be transmitted through the same path as the functional reset path, utilizing a target reset controller synchronized with the functional clock to ensure comprehensive testing of all components and IP blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a separate test reset path is used for testing, then test setup is simplified, but test coverage of functional reset paths is reduced
Solution Approach 1:
The reset controller is designed to perform multiple functions: it generates both functional reset signals during normal operation and test reset signals during testing. The same reset path and controller resources are utilized for both functional operation and test operation, eliminating the need for separate dedicated test paths while maintaining full test coverage of the functional reset infrastructure.
2Reliability
If dedicated test reset paths are created, then test isolation is improved, but device complexity increases
Solution Approach 1:
The reset controller dynamically switches between functional mode and test mode based on operational requirements. During functional operation, it generates normal reset signals through the functional reset path. During testing, it generates test reset signals while utilizing the same physical path, achieving test isolation through temporal separation and mode control rather than through separate physical paths.
3Measurement precision
If functional reset paths are tested separately from test reset paths, then functional verification is improved, but test time increases
Solution Approach 1:
The testing methodology merges functional verification and test reset verification into a single integrated process. By using the same reset path for both functional operation and testing, the patent enables simultaneous verification of functional correctness and reset path integrity without requiring separate test sequences, thereby reducing total test time while maintaining comprehensive verification.
Data Source
AI summary
A reset test system includes: a scan test controller that generates a scan test enable signal indicating whether a scan test mode is activated, a scan reset control signal controlling reset in the scan test mode, and a scan reset deactivation signal controlling the reset to be deactivated in the scan test mode; a target reset test controller that generates a target reset test mode signal indicating whether a target is in a test mode and target reset test data; and a target reset controller that receives the scan test enable signal, the scan reset control signal, the scan reset deactivation signal, the target reset test mode signal, the target reset test data, reset input, and a functional clock of the target, outputs the reset input in synchronization with the functional clock, and outputs the target reset test data when the reset is activated in the scan test mode.