SoC Gate Contact Structure for Multigate Transistor Scaling

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Solution Overview

Problem

Current multigate transistor designs face challenges in scaling and controlling short channel effects due to limitations in gate length and complexity of cross-coupling node structures, which affect the efficiency and performance of semiconductor devices.

Innovation Solution

The implementation of a system on chip (SoC) with a 3-contacted poly pitch cross-coupling node using a gate contact structure, where gate lines are cut and electrically connected through metal lines, simplifying the structure and enhancing performance by reducing complexity and stress effects on source and drain regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional multigate transistor designs are used, then three-dimensional channel control is achieved, but device complexity and stress effects on source and drain regions increase

Engineering Contradiction:
Improveelectric current control abilityVSAvoidcross-coupling node structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The gate line is segmented into multiple portions (first gate line portion, second gate line portion, third gate line portion) separated by isolation regions. Each segment is independently connected to gate electrodes, allowing simplified cross-coupling node structure while maintaining effective gate control over the three-dimensional channel.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Isolation regions are introduced as intermediary elements between gate line portions and between active fins. These isolation regions electrically isolate different gate segments and reduce stress transmission to source and drain regions, thereby reducing device complexity and stress effects.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If gate length is increased to control short channel effects, then electric potential control is improved, but scaling capability is reduced

Engineering Contradiction:
Improveshort channel effect controlVSAvoidgate length
Core Design Contradiction:
ReliabilityVSLength of moving object

Solution Approach 1:

The patent transitions from planar gate control to three-dimensional gate control by wrapping gate electrodes around active fins in vertical and lateral dimensions. This multigate structure provides superior electric potential control over the channel without requiring increased gate length, enabling effective short channel effect control while maintaining scaling capability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Multiple gate electrodes are nested around the active fin structure, with gate lines wrapping around fins in a nested configuration. This nested multigate structure enhances control over the three-dimensional channel, improving short channel effect control without increasing gate length.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Ease of manufacture

If cross-coupling node structure is simplified, then manufacturing ease is improved, but electric current control ability may be compromised

Engineering Contradiction:
Improvecross-coupling node structure simplicityVSAvoidelectric current control ability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The gate line structure serves multiple functions: it provides electrical connection to gate electrodes, acts as an isolation structure through embedded isolation regions, and enables simplified cross-coupling node formation. This multi-functional design simplifies manufacturing while maintaining effective electric current control through the three-dimensional channel.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The isolation regions are merged into the gate line structure itself, combining the isolation function with the gate electrode connection function. This merging simplifies the cross-coupling node structure and manufacturing processes while maintaining effective gate control over the channel.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10541237B2System on chip
Publication Date: 2020.01.21 SAMSUNG ELECTRONICS CO LTD
  • US10541237B2 patent drawing
  • US10541237B2 patent drawing
  • US10541237B2 patent drawing

AI summary

A method is provided. The method includes forming a first to third gate lines on a substrate, the second gate line formed between the first and third gate lines; forming a gate isolation region to cut the first to third gate lines into two first sub gate lines, two second sub gate lines and two third sub gate lines, respectively; forming a first gate contact on one of the two first sub gate lines; forming a second gate contact on the two second sub gate lines; forming a third gate contact on one of the two third sub gate lines; forming a first metal line to connect the first and third gate contacts; and forming a second metal line. The first to third gate lines extend in a first direction, and the gate isolation region extends in a second direction different from the first direction.