SOC Gate Metal Via Pitch Alignment
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Solution Overview
Problem
Achieving optimal cost, power, and performance benefits through pitch scaling in system on a chip (SOC) design is hindered by the requirement for area scaling, as existing methods do not align via pitch with gate and metal interconnect pitches, leading to inefficiencies in pin access and place and route utilization.
Innovation Solution
The SOC apparatus includes gate interconnects, metal interconnects, and vias with specific pitch relationships, where the gate and metal interconnect pitches are adjusted to satisfy the condition g² + m² ≥ v², and the least common multiple (LCM) of the gate and metal interconnect pitches is less than 20 times the gate pitch, ensuring improved alignment and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If pitch scaling is applied to achieve area scaling, then cost and power benefits are improved, but alignment between via pitch and gate/metal interconnect pitches deteriorates
Solution Approach 1:
The patent changes the pitch parameters of gate interconnects, metal interconnects, and vias to satisfy specific mathematical relationships (g² + m² ≥ v² and LCM(g, m) < 20g). This parameter optimization allows pitch scaling to achieve power and cost benefits while maintaining proper alignment between different interconnect layers, resolving the contradiction between energy efficiency and manufacturing precision.
2Area of stationary object
If traditional pitch scaling methods are used, then area reduction is achieved, but pin access efficiency and place and route utilization worsen
Solution Approach 1:
The patent optimizes pitch parameters to satisfy g² + m² ≥ v² and LCM(g, m) < 20g, which ensures that as the chip area is reduced through scaling, the alignment between gate, metal, and via pitches remains coherent. This prevents degradation of pin access efficiency and place and route utilization, allowing area reduction without sacrificing productivity.
3Area of stationary object
If gate and metal interconnect pitches are independently scaled, then area scaling is achieved, but alignment between interconnect layers deteriorates
Solution Approach 1:
The patent establishes mathematical relationships between gate pitch (g), metal pitch (m), and via pitch (v) where g² + m² ≥ v² and LCM(g, m) < 20g. These parameter constraints ensure that when pitches are scaled, the relative alignment between gate, metal, and via layers remains stable and manufacturable, preventing composition instability during scaling.
Data Source
AI summary
An SOC apparatus includes a plurality of gate interconnects with a minimum pitch g, a plurality of metal interconnects with a minimum pitch m, and a plurality of vias interconnecting the gate interconnects and the metal interconnects. The vias have a minimum pitch v. The values m, g, and v are such that g 2+m 2≥v 2 and an LCM of g and m is less than 20g. The SOC apparatus may further include a second plurality of metal interconnects with a minimum pitch of m2, where m2 > m and the LCM of g, m, and m 2 is less than 20g.