SoC Error Management With Grouped Test-Error Reactions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional error management systems in system-on-chip (SoC) execute the same number of processing cycles for both injected test errors and functional errors, leading to reduced availability of functional operations due to instant reactions, and the circuits remain unavailable during these reactions.
Innovation Solution
The error management system differentiates between injected test errors and functional errors, generating a single reaction for multiple test errors associated with the same reaction, thereby reducing the number of processing cycles and increasing the availability of functional circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the error management system executes instant reactions for every detected error (both test errors and functional errors), then the error detection reliability is improved, but the number of processing cycles increases and functional circuit availability decreases
Solution Approach 1:
The patent segments the error handling process by introducing a test error indicator that distinguishes between test errors and functional errors. This segmentation allows the system to apply different reaction strategies: test errors are grouped and handled collectively, while functional errors receive immediate attention, thus resolving the contradiction between reliable error detection and maintaining functional circuit availability
Solution Approach 2:
The system performs preliminary action by setting a test error indicator before injecting test errors. This preliminary marking enables the error management system to identify and group test errors separately from functional errors, allowing batch processing of test errors without impacting functional circuit operations, thereby maintaining both reliability and productivity
2Measurement precision
If the error management system generates a reaction signal for every injected test error, then the error detection capability is validated, but the number of processing cycles increases unnecessarily
Solution Approach 1:
The patent merges multiple test error detections into a single reaction by using the test error indicator to group them. Instead of generating separate reaction signals for each test error, the system accumulates test errors with the same indicator and generates one consolidated reaction signal, thereby validating error detection capability while minimizing processing cycle loss
Solution Approach 2:
The system changes the parameter of error handling by introducing the test error indicator as a new parameter. This parameter enables the system to differentiate between test errors and functional errors, allowing test errors to be processed in batches with a single reaction signal, thus reducing processing cycles while maintaining detection validation
Data Source
Figure 1
Figure 2
AI summary
An error management system can include register sets associated with an error reaction. The test errors are injected in functional signals based on activation of multiple bits in one of the register sets. When the functional signals with the injected test errors are received by the error management system, multiple bits in the other register set are activated. The error management system generates an activated indication signal when a number of the activated bits in one register set matches a number of activated bits in the other register set. When the indication signal is activated, the error management system generates a reaction signal indicative of the error reaction. Thus, the error management system generates a single reaction signal in response to the injected test errors requiring the same reaction.