Hardware Software Co-synthesis Latency Estimation
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Solution Overview
Problem
Designing a system-on-chip (SOC) is challenging due to the difficulty in determining which portions of the design should be hardware accelerated, as testing alternative architectures by implementing in hardware is time-consuming, making evaluation infeasible for complex designs.
Innovation Solution
A method that estimates hardware latency for hardware accelerator implementations by scheduling and generating latency information, compiling an instrumented design, and combining hardware and software latency to determine design performance without full hardware implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If alternative architectures are tested by implementing in hardware, then design performance accuracy is improved, but design time and productivity deteriorate
Solution Approach 1:
The patent creates a virtual model (copy) of the hardware accelerator and its interaction with the processor. This virtual model includes a hardware latency model that simulates hardware execution time and a software latency model that measures actual processor execution time. By using this copy instead of physical hardware implementation, the system achieves accurate performance estimation without the time-consuming process of actual hardware testing.
Solution Approach 2:
The patent performs preliminary characterization of both hardware and software latency components before final design decisions are made. The hardware latency model is built in advance based on the hardware accelerator architecture, and the software latency is measured during compilation and linking. This preliminary action allows performance evaluation to occur early in the design process, avoiding the need for time-consuming post-implementation hardware testing.
2Speed
If hardware acceleration is implemented for complex designs, then processing speed is improved, but design complexity and testing time increase
Solution Approach 1:
The patent segments the design performance evaluation into distinct components: hardware latency model, software latency model, and combined performance model. This segmentation allows each component to be analyzed and optimized independently. The hardware accelerator can be designed and characterized separately from the processor software, enabling parallel development and reducing overall design complexity despite the speed improvements achieved through hardware acceleration.
Data Source
AI summary
Hardware and software co-synthesis performance estimation includes, for a design specified in a high level programming language and having a processor executable partition and a partition selected for hardware acceleration, estimating hardware latency for a hardware accelerator implementation of the selected partition, scheduling the selected partition using the hardware latency generating hardware partition latency information, and compiling an instrumented version of the design using a processor. The instrumented and compiled version of the design is executed generating software latency information. A design performance for the design is determined through combining the hardware partition latency information with the software latency information.